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path: root/drivers/gpu/drm/amd/amdgpu
AgeCommit message (Expand)AuthorFilesLines
2020-10-30amdgpu: Add GFX MGCG and MGLS for vangoghJinzhou.Su1-1/+5
2020-10-30drm/amdgpu: fix the issue of reserving bad pages failedDennis Li4-119/+156
2020-10-30drm/amdgpu: remove redundant GPU resetDennis Li2-25/+1
2020-10-30drm/amdgpu: change to save bad pages in UMC error interrupt callbackDennis Li3-7/+6
2020-10-30drm/amdgpu: rename nv_is_headless_sku()Flora Cui1-3/+3
2020-10-30drm/amdgpu: disable DCN and VCN for Navi14 0x7340/C9 SKUFlora Cui1-2/+3
2020-10-29drm/amdgpu: switch to new allocator v2Christian König1-31/+14
2020-10-29drm/ttm: wire up the new pool as default one v2Christian König1-2/+2
2020-10-27drm/amdgpu: drop mem_global_referencedChristian König1-1/+0
2020-10-27drm/amdgpu: add vangogh apu flagHuang Rui1-1/+3
2020-10-27drm/amdgpu: enable MULTI_MON_PP_MCLK_SWITCH DC feature at defaultEvan Quan1-2/+10
2020-10-27drm/amdgpu: correct CG_ACLK_CNTL settingEvan Quan1-3/+11
2020-10-27drm/amd/pm: correct the checks for polaris kickersEvan Quan3-49/+48
2020-10-27drm/amdgpu: increase the reserved VM size to 2MBChristian König1-2/+2
2020-10-27drm/amdgpu: don't map BO in reserved regionMadhav Chauhan1-0/+10
2020-10-27drm/amdgpu: add DID for navi10 blockchain SKUTianci.Yin1-0/+1
2020-10-27drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)Tianci.Yin1-2/+12
2020-10-26drm/amdgpu: use true and false for bool initialisationsSumera Priyadarsini1-1/+1
2020-10-26drm/amdgpu: Discard unnecessary breaksZhang Qilong3-17/+0
2020-10-26drm/amdgpu: nuke amdgpu_vm_bo_split_mapping v2Christian König1-103/+79
2020-10-26drm/amdgpu: increase the reserved VM size to 2MBChristian König1-2/+2
2020-10-26drm/amdgpu: added support for psp fw attestationJohn Clements7-20/+250
2020-10-26drm/amdgpu: enable IP discovery for vangoghXiaomeng Hou1-4/+0
2020-10-26drm/ttm: merge ttm_dma_tt back into ttm_ttChristian König3-20/+11
2020-10-26drm/ttm: make num_pages uint32_tChristian König1-5/+5
2020-10-26drm/ttm: nuke ttm_tt_set_(un)populated againChristian König1-2/+0
2020-10-23Merge tag 'drm-next-2020-10-23' of git://anongit.freedesktop.org/drm/drmLinus Torvalds8-12/+143
2020-10-23drm/amdgpu: Fix size calculation when init onchip memoryxinhui pan1-2/+2
2020-10-23drm/amdgpu: fix some kernel-doc markupsMauro Carvalho Chehab2-2/+2
2020-10-23amdgpu: fix a few kernel-doc markup issuesMauro Carvalho Chehab1-3/+5
2020-10-23drm/amdgpu: During compute disable GFXOFF for Sienna_CichlidHarish Kasiviswanathan1-0/+7
2020-10-23drm/amdgpu: don't map BO in reserved regionMadhav Chauhan1-0/+10
2020-10-23drm/amdgpu: add support to configure MALL for sienna_cichlid (v2)Likun Gao3-2/+6
2020-10-23drm/amdgpu: add DID for navi10 blockchain SKUTianci.Yin1-0/+1
2020-10-23drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)Tianci.Yin1-2/+12
2020-10-23drm/amdgpu: correct the cu and rb info for sienna cichlidLikun Gao1-0/+9
2020-10-22drm/amdgpu: correct the cu and rb info for sienna cichlidLikun Gao1-0/+9
2020-10-22Revert drm/amdgpu: disable sienna chichlid UMC RASJohn Clements1-2/+2
2020-10-22drm/ttm: replace last move_notify with delete_mem_notifyDave Airlie1-1/+7
2020-10-22drm/amd/psp: Fix sysfs: cannot create duplicate filenameAndrey Grodzovsky1-1/+2
2020-10-22drm/amdgpu: update golden setting for sienna_cichlidLikun Gao1-0/+1
2020-10-22drm/amdgpu: correct the gpu reset handling for job != NULL caseEvan Quan1-1/+1
2020-10-22drm/amdgpu: add rlc iram and dram firmware supportLikun Gao6-8/+66
2020-10-22drm/amdgpu: add function to program pbb mode for sienna cichlidLikun Gao1-0/+62
2020-10-21drm: amdgpu: kernel-doc: update some adev parametersMauro Carvalho Chehab3-21/+20
2020-10-21Revert drm/amdgpu: disable sienna chichlid UMC RASJohn Clements1-2/+2
2020-10-21drm/amdgpu/gmc10: remove dummy read workaround for newer chipsAlex Deucher1-2/+4
2020-10-21drm/amd/amdgpu: enable noretry for Sienna_Cichlid/Navy_Flounder/Dimgrey_CavefishChengming Gui1-0/+3
2020-10-21drm/amdgpu: enable VCN PG and CG for vangoghBoyuan Zhang1-2/+7
2020-10-21drm/amdgpu: protect eeprom update from GPU resetDennis Li1-0/+8
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