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path: root/drivers/gpu/drm/amd/amdgpu
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2019-07-18drm/amdgpu/dce_virtual: add Arcturus virtual display supportLe Ma1-0/+1
Virtual dce is a sw only display driver for emulation and virtualization and cases where we want to use a virtual display subsystem. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: set Arcturus fw load type as directLe Ma1-0/+2
We currently only support direct firmware loading. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add to set Arcturus ip blocksLe Ma1-0/+1
Add IP blocks for Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/soc15: add Arcturus common ip blocksLe Ma1-2/+16
Add common IP blocks for Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: support hdp flush for more sdma instancesLe Ma3-4/+24
The bit RSVD_ENG0 to RSVD_ENG5 in GPU_HDP_FLUSH_REQ/GPU_HDP_FLUSH_DONE can be leveraged for sdma instance 2~7 to poll register/memory. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: specify sdma instance 5~7 with second mmhub typeLe Ma1-1/+42
On Arcturus, sdma instance 5~7 is connected to the second mmhub. The vmhub type in amdgpu_ring_funcs is constant, so we create an individual amdgpu_ring_funcs with different vmhub type(AMDGPU_MMHUB_1) for these sdma instances. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: reorganize sdma v4 code to support more instancesLe Ma2-45/+107
This change is needed for Arcturus which has 8 sdma instances. The CG/PG part is not covered for now. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: update vmc interrupt routine to support 3 vmhubsLe Ma1-3/+14
There is one more vmc interrupt and mmhub on Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add VMC1 interrupt client id for ArcturusLe Ma1-0/+7
New IH client id for VMC1. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: dynamically initialize IP offset for ArcturusLe Ma4-1/+63
Add support for the IP offsets on Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: increase max number of ip base instances to 8Le Ma1-1/+1
For Arcturus, the number of IP base instances is 8. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add SDMA 2~7 ip block typeLe Ma1-0/+6
Add IP block type. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: use new mmhub interfaces for ArcturusLe Ma1-6/+29
Arcturus has two MMHUBs. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add mmhub v9.4.1 block for Arcturus (v2)Le Ma3-1/+538
Arcturus as an updated mmhub block. mmhub is the memory controller hub used for sdma and multimedia. v2: squash in AGP BAR programming (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add one more mmhub instance for Arcturus (v2)Le Ma2-2/+7
v2: set mmhub num under CHIP_ARCTURUS switch case and add one more mmhub id_mgr Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add new member in amdgpu_device for vmhub counts per asic chipLe Ma3-3/+9
It aims to replace AMDGPU_MAX_VMHUBS in for loop to initialize registers. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub numberLe Ma16-46/+46
The number of GFXHUB/MMHUB may be expanded in later ASICs. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add gmc basic support for ArcturusLe Ma1-0/+5
Add initial GMC support for Arcturus Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add Arcturus asic typeLe Ma1-0/+1
Add asic type for Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: consolidate navi14 IP initAlex Deucher1-15/+1
It's the same as navi10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: disable concurrent flushes on Navi14Alex Deucher1-1/+2
Same thing applies to navi14 as navi10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: enable gfxoff code path for navi14Jack Xiao2-3/+2
Based on navi10 gfxoff logic, enable the related code path for navi14. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/vcn: enable indirect DPG SRAM mode for navi14Xiaojie Yuan2-1/+5
Enable VCN dynamic powergating for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/nv: set vcn pg flag for navi14Xiaojie Yuan1-1/+1
Enable VCN power gating by default. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: enable async gfx ring for navi14Xiaojie Yuan1-3/+3
Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: enable clock gatings for navi14Xiaojie Yuan1-1/+14
Set appropriate CG flags for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/athub2: set clock gating for navi14Xiaojie Yuan1-0/+1
same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/mmhub2: set clock gating for navi14Xiaojie Yuan1-0/+1
same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: declare asd firmware for navi14Xiaojie Yuan1-0/+1
So the dependency gets properly tracked. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <snow.zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: Enable VCN on navi14James Zhu2-0/+6
Add navi14 vcn firmware, and enable VCN on navi14. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: skip to load ta firmware for navi14Xiaojie Yuan1-0/+1
Not relevant on navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: add dm blockBhawanpreet Lakha2-0/+3
enable DC for navi14. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: enable sw smu ip for navi14Xiaojie Yuan1-0/+2
same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/psp: start rlc autoload after psp received rlcg for navi14Xiaojie Yuan1-1/+3
Update for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: enable psp ip block for navi14Xiaojie Yuan1-0/+1
Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/psp: add psp support for navi14 (v3)Xiaojie Yuan2-0/+5
Same as navi10. v2: squash in logic fix (Colin Ian King) v3: squash in logic simplification (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: enable virtual display for navi14Xiaojie Yuan2-0/+3
Virtual display is a sw based kms interface for virtualization and emulation. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add ip blocks for navi14Xiaojie Yuan1-0/+7
Add the initial IP blocks for navi14 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/soc15: add support for navi14Xiaojie Yuan1-0/+6
same as navi10 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/gfx10: fix programming of SC_HIZ_TILE_FIFO_SIZE fieldJack Xiao1-1/+1
max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE field is programmed in units of two entries, but 6 bits is insufficient to hold value 128/2 = 64, so set this field as 0 which is interpreted by the hardware as maximum physical fifo size(128). Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/gfx10: update gfx golden settings for navi14Tao Zhou1-4/+4
Updated settings from hw team. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/gfx10: update gfx golden settings for navi14Xiaojie Yuan1-3/+5
Add updated settings from hw team. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/gfx: update gc_v10_1_1 golden settingXiaojie Yuan1-1/+1
Updated settings for hw team. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/gfx10: add gfx v10_1_1 golden settings for navi14Xiaojie Yuan1-2/+40
Add golden settings for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/gfx: add definition of mmCGTT_GS_NGG_CLK_CTRLXiaojie Yuan1-0/+3
Needed for clockgating. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/gfx10: set tcp harvest for navi14Xiaojie Yuan1-1/+3
Update settings for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: set rlc funcs for navi14Xiaojie Yuan1-0/+1
Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add me/mec configurations for navi14Xiaojie Yuan1-0/+1
Add navi14 to appropriate cases. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/gfx10: add clockgating support for navi14Xiaojie Yuan1-0/+1
Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu/gfx10: add gfx config for navi14Xiaojie Yuan1-0/+8
Add gfx config details for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 02:38:54 +0300