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path: root/drivers/gpu/drm/amd/amdgpu
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2019-08-23drm/amdgpu: enable athub clock gating for rnPrike Liang1-1/+3
Enable athub MG and LS clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: enable IH clock gating for rnPrike Liang1-1/+2
Enable IH clock gating during IH block initialized. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: enable vcn clock gating for rnPrike Liang1-1/+2
Enable VCN middle grain clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: enable rom clock gating for rnPrike Liang1-1/+2
Enable rom light sleep clock gating. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: enable HDP clock gating for rnPrike Liang1-1/+2
Enable HDP light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: enable BIF clock gating for rnPrike Liang1-1/+2
Enable BIF light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: enable sdma clock gating for rnPrike Liang1-1/+3
Enable sdma middle grain and light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: enable mmhub clock gating for rnPrike Liang1-1/+3
Enable mmhub midle grain and light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: enable gfx clock gating for rnPrike Liang1-1/+7
Enable gfx cg/mg/cp etc clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: add and enable gfxoff featureAaron Liu1-0/+5
This patch updates gfxoff feature. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: add set_gfx_cgpg implement (v2)Aaron Liu1-0/+5
add set_gfx_cgpg implement v2: check if using sw_smu (Alex) Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoirAaron Liu1-2/+2
1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir 2.adjust smu ip block ahead of gfx&sdma ip block Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu/powerplay: add smu ip block for renoir (v2)Aaron Liu1-0/+2
add swSMU [smu_v12_0] for renoir v2: whitespace fixes (Alex) Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1xXiaojie Yuan1-1/+2
v2: set num_types based on num_instances navi1x has 2 sdma engines but commit "e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances" changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8 which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma engines with following logic: (enable irq for sdma0) * 1 time (enable irq for sdma1) * 1 time (disable irq for sdma1) * 6 times as a result, after gpu reset, interrupt for sdma1 is lost. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: fix dma_fence_wait without referenceChristian König1-12/+15
We need to grab a reference to the fence we wait for. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23amd/amdgpu: add Arcturus vf DID supportFrank.Min1-0/+1
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Frank.Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: unity mc base address for arcturusFrank.Min1-6/+6
arcturus for sriov would use the unified mc base address Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Frank.Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu: disable agp for sriovFrank.Min2-2/+9
Since agp is not used for sriov, just disable it Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Frank.Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu: remove duplicated include from gfx_v9_0.cYueHaibing1-1/+0
Remove duplicated include. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu: remove set but not used variable 'psp_enabled'YueHaibing1-5/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_common_early_init': drivers/gpu/drm/amd/amdgpu/nv.c:471:7: warning: variable 'psp_enabled' set but not used [-Wunused-but-set-variable] It's not used since inroduction in commit c6b6a42175f5 ("drm/amdgpu: add navi10 common ip block (v3)") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu: prevent memory leaks in AMDGPU_CS ioctlNicolai Hähnle1-2/+7
Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the allocated array as well as the reference counts of sync objects are leaked. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amd/amdgpu: disable MMHUB PG for navi10Kenneth Feng1-1/+0
Disable MMHUB PG for navi10 according to the production requirement. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amd/powerplay: expose supported clock domains only through sysfsEvan Quan1-10/+16
Do not expose those unsupported clock domains through sysfs on Arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu/psp: move TMR to cpu invisible vram regionTianci.Yin3-5/+5
so that more visible vram can be available for umd. Reviewed-by: Christian König <christian.koenig@amd.com>. Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu: remove redundant argument for psp_funcs::cmd_submit callbackXiaojie Yuan6-9/+3
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu: Set no-retry as default.Feifei Xu1-2/+2
This is to improve performance. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Tested-by: Candice Li <candice.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu: add firmware header printing for psp fw loading (v2)Xiaojie Yuan1-0/+56
firmware header information is printed for direct fw loading but not added for psp fw loading yet v2: squash in warning fix (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu: fix debug level for ppt offset/sizeXiaojie Yuan1-2/+2
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu: remove special autoload handling for navi12Xiaojie Yuan1-2/+1
s/r list in rlc firmware is ready, so remove the special autoload handling Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possibleAlex Deucher2-5/+4
We need to set certain power gating flags after we determine if the firmware version is sufficient to support gfxoff. Previously we set the pg flags in early init, but we later we might have disabled gfxoff if the firmware versions didn't support it. Move adding the additional pg flags after we determine whether or not to support gfxoff. Fixes: 005440066f92 ("drm/amdgpu: enable gfxoff again on raven series (v2)") Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Tested-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
2019-08-22Merge branch 'odp_fixes' into hmm.gitJason Gunthorpe13-74/+196
From rdma.git Jason Gunthorpe says: ==================== This is a collection of general cleanups for ODP to clarify some of the flows around umem creation and use of the interval tree. ==================== The branch is based on v5.3-rc5 due to dependencies, and is being taken into hmm.git due to dependencies in the next patches. * odp_fixes: RDMA/mlx5: Use odp instead of mr->umem in pagefault_mr RDMA/mlx5: Use ib_umem_start instead of umem.address RDMA/core: Make invalidate_range a device operation RDMA/odp: Use kvcalloc for the dma_list and page_list RDMA/odp: Check for overflow when computing the umem_odp end RDMA/odp: Provide ib_umem_odp_release() to undo the allocs RDMA/odp: Split creating a umem_odp from ib_umem_get RDMA/odp: Make the three ways to create a umem_odp clear RMDA/odp: Consolidate umem_odp initialization RDMA/odp: Make it clearer when a umem is an implicit ODP umem RDMA/odp: Iterate over the whole rbtree directly RDMA/odp: Use the common interval tree library instead of generic RDMA/mlx5: Fix MR npages calculation for IB_ACCESS_HUGETLB Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2019-08-21Merge tag 'drm-misc-next-2019-08-19' of ↵Dave Airlie17-69/+69
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.4: UAPI Changes: Cross-subsystem Changes: Core Changes: - dma-buf: add reservation_object_fences helper, relax reservation_object_add_shared_fence, remove reservation_object seq number (and then restored) - dma-fence: Shrinkage of the dma_fence structure, Merge dma_fence_signal and dma_fence_signal_locked, Store the timestamp in struct dma_fence in a union with cb_list Driver Changes: - More dt-bindings YAML conversions - More removal of drmP.h includes - dw-hdmi: Support get_eld and various i2s improvements - gm12u320: Few fixes - meson: Global cleanup - panfrost: Few refactors, Support for GPU heap allocations - sun4i: Support for DDC enable GPIO - New panels: TI nspire, NEC NL8048HL11, LG Philips LB035Q02, Sharp LS037V7DW01, Sony ACX565AKM, Toppoly TD028TTEC1 Toppoly TD043MTEA1 Signed-off-by: Dave Airlie <airlied@redhat.com> [airlied: fixup dma_resv rename fallout] From: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190819141923.7l2adietcr2pioct@flea
2019-08-20hmm: use mmu_notifier_get/put for 'struct hmm'Jason Gunthorpe1-0/+2
This is a significant simplification, it eliminates all the remaining 'hmm' stuff in mm_struct, eliminates krefing along the critical notifier paths, and takes away all the ugly locking and abuse of page_table_lock. mmu_notifier_get() provides the single struct hmm per struct mm which eliminates mm->hmm. It also directly guarantees that no mmu_notifier op callback is callable while concurrent free is possible, this eliminates all the krefs inside the mmu_notifier callbacks. The remaining krefs in the range code were overly cautious, drivers are already not permitted to free the mirror while a range exists. Link: https://lore.kernel.org/r/20190806231548.25242-6-jgg@ziepe.ca Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Ralph Campbell <rcampbell@nvidia.com> Tested-by: Ralph Campbell <rcampbell@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2019-08-16dma-buf: Restore seqlock around dma_resv updatesChris Wilson1-1/+6
This reverts 67c97fb79a7f ("dma-buf: add reservation_object_fences helper") dd7a7d1ff2f1 ("drm/i915: use new reservation_object_fences helper") 0e1d8083bddb ("dma-buf: further relax reservation_object_add_shared_fence") 5d344f58da76 ("dma-buf: nuke reservation_object seq number") The scenario that defeats simply grabbing a set of shared/exclusive fences and using them blissfully under RCU is that any of those fences may be reallocated by a SLAB_TYPESAFE_BY_RCU fence slab cache. In this scenario, while keeping the rcu_read_lock we need to establish that no fence was changed in the dma_resv after a read (or full) memory barrier. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190814182401.25009-1-chris@chris-wilson.co.uk
2019-08-15drm/amdgpu: Use new mode2 reset interface for RV.Andrey Grodzovsky2-8/+18
Integrate the mode2 reset into rest sequence. v2: Check ppfuncs pointer for NULL Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15dmr/amdgpu: Fix compile error with CONFIG_DRM_AMDGPU_GART_DEBUGFSAndrey Grodzovsky1-1/+1
Double defintion of 'i' Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/amdgpu: Update VM function pointerGang Ba1-0/+7
When VM state changed and system in large bar mode, make sure to use CPU update function, otherwise use SDMA function. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Gang Ba <gaba@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0 for GFX10Yong Zhao2-2/+2
We have done this for pre-GFX10 asics, but GFX10 did not pick up the new change. The below is the commit message for that change. This is recommended by HW designers. Previously when it was set to 1, the PDE walk error in VM fault will be treated as PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT. As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly. The above behavior is kind of abnormal. Furthermore, the PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs and it never made it way to production. Therefore, we should set it to 0. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: Add more page fault info printing for GFX10Yong Zhao1-5/+28
The printing we did for GFX9 was not propogated to GFX10 somehow, so fix it now. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: Add printing for RW extracted from VM_L2_PROTECTION_FAULT_STATUSYong Zhao1-0/+3
RW is also useful in most cases. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdkfd/gfx10: Calling amdgpu functions to invalidate TLBOak Zeng1-38/+3
Calling amdgpu function to invalidate TLB, instead of using a kfd implementation. Delete the kfd local TLB invalidation implementation. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: Export function to flush TLB of specific vm hubOak Zeng9-57/+78
This is for kfd to reuse amdgpu TLB invalidation function. On gfx10, kfd only needs to flush TLB on gfx hub but not on mm hub. So export a function for KFD flush TLB only on specific hub. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: MODULE_FIRMWARE requires linux/module.hStephen Rothwell1-0/+1
Fixes: 6a7a0bdbfa0c ("drm/amdgpu: add psp_v12_0 for renoir (v2)") Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: implement querying ras error count for mmhubTao Zhou1-0/+55
get mmhub ea ras error count by accessing EDC_CNT register Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: use exiting amdgpu_ctx_total_num_entities functionKevin Wang1-4/+1
simplify driver code. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: fix typo error amdgput -> amdgpuKevin Wang1-6/+6
fix typo error: change function name from "amdgput_ctx_total_num_entities" to "amdgpu_ctx_total_num_entities". Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: simplify and cleanup setting the dma maskChristoph Hellwig6-83/+14
Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: handle PCIe root ports with addressing limitationsChristoph Hellwig1-1/+1
amdgpu uses a need_dma32 flag to indicate to the drm core that some allocations need to be done using GFP_DMA32, but it only checks the device addressing capabilities to make that decision. Unfortunately PCIe root ports that have limited addressing exist as well. Use the dma_addressing_limited instead to also take those into account. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-13dma-buf: rename reservation_object to dma_resvChristian König17-67/+67
Be more consistent with the naming of the other DMA-buf objects. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/323401/
2019-08-13drm/amdgpu: fix gfx9 soft recoveryPierre-Eric Pelloux-Prayer1-1/+1
The SOC15_REG_OFFSET() macro wasn't used, making the soft recovery fail. v2: use WREG32_SOC15 instead of WREG32 + SOC15_REG_OFFSET Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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