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path: root/drivers/gpu/drm/amd/amdgpu
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2019-08-07Revert "drm/amdgpu: fix transform feedback GDS hang on gfx10 (v2)"Marek Olšák2-12/+1
This reverts commit 9ed2c993d723129f85101e51b2ccc36ef5400a67. SET_CONFIG_REG writes to memory if register shadowing is enabled, causing a VM fault. NGG streamout is unstable anyway, so all UMDs should use legacy streamout. I think Mesa is the only driver using NGG streamout. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amdgpu: pin the csb buffer on hw init for gfx v8Likun Gao1-0/+40
Without this pin, the csb buffer will be filled with inconsistent data after S3 resume. And that will causes gfx hang on gfxoff exit since this csb will be executed then. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Tested-by: Paul Gover <pmw.gover@yahoo.co.uk> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amdgpu: Fix GPU reset crash regression.Andrey Grodzovsky1-0/+2
amdgpu_ip_block.status.hw for GMC wasn't set to false on suspend during GPU reset and so on resume gmc_v9_0_resume wasn't called. Caused by 'drm/amdgpu: fix double ucode load by PSP(v3)' Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init()Xiaojie Yuan3-28/+29
move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a common function nv_reg_base_init(). Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amdgpu/soc15: fix external_rev_id for navi14tiancyin1-1/+1
fix the hard code external_rev_id. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amdgpu: update ras sysfs feature infoTao Zhou1-12/+5
remove confused ras error type info Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amdgpu: Fix panic during gpu resetxinhui pan1-1/+1
Clear the flag after hw suspend, otherwise it skips the corresponding hw resume. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amdgpu: pin the csb buffer on hw init for gfx v8Likun Gao1-0/+40
Without this pin, the csb buffer will be filled with inconsistent data after S3 resume. And that will causes gfx hang on gfxoff exit since this csb will be executed then. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Tested-by: Paul Gover <pmw.gover@yahoo.co.uk> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amdgpu: switch driver from bo->resv to bo->base.resvGerd Hoffmann12-48/+46
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: http://patchwork.freedesktop.org/patch/msgid/20190805140119.7337-14-kraxel@redhat.com
2019-08-06drm/ttm: use gem vma_nodeGerd Hoffmann1-1/+1
Drop vma_node from ttm_buffer_object, use the gem struct (base.vma_node) instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: http://patchwork.freedesktop.org/patch/msgid/20190805140119.7337-9-kraxel@redhat.com
2019-08-06drm/amdgpu: use embedded gem objectGerd Hoffmann6-13/+12
Drop drm_gem_object from amdgpu_bo, use the ttm_buffer_object.base instead. Build tested only. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: http://patchwork.freedesktop.org/patch/msgid/20190805140119.7337-6-kraxel@redhat.com
2019-08-05dma-buf: add more reservation object locking wrappersChristian König4-8/+9
Complete the abstraction of the ww_mutex inside the reservation object. This allows us to add more handling and debugging to the reservation object in the future. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/320761/
2019-08-02drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec ring test to vcn_v2_0Thong Thai1-1/+31
VCN 2.0 firmware now requires a packet start command to be sent before any other decode ring buffer command. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commandsThong Thai2-6/+7
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: enable Navi12 kfd support for amdgpushaoyunl1-0/+1
Navi12 has the same interface as Navi10 Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: Add nv12 DC ip blockLeo Li2-0/+3
Load DC and amdgpu display manager Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: enable DPG mode for Navi12Boyuan Zhang1-1/+1
Enable Dynamic Power Gating VCN for Navi12. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: add VCN ip block for Navi12Boyuan Zhang1-0/+1
Add VCN2 ip block for Navi12 Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: add Navi12 VCN firmware supportBoyuan Zhang1-1/+9
Add Navi12 to VCN family Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: add psp ip block for navi12Xiaojie Yuan1-0/+1
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: add smu ip block for navi12Xiaojie Yuan1-0/+6
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: start autoload till RLCG fw for navi12Xiaojie Yuan1-1/+2
rlc save restore list is not ready yet for navi12 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/psp11: add psp support for navi12Xiaojie Yuan2-0/+7
Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: correct smu rlc handshake enablement bitJack Xiao1-2/+2
Correct the enablement bit of SMU RLC handshake. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/sdma5: add golden settings for navi12 (v2)Xiaojie Yuan1-0/+2
common golden settings are put in golden_settings_sdma_5 array v2: update settings (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/gfx10: add golden settings for navi12 (v2)Xiaojie Yuan1-5/+49
Add initial golden settings for navi12 gfx. v2: update settings Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: enable virtual display for navi12Xiaojie Yuan2-0/+3
Virtual display is a sw display interface for bring up and virtualization or for cards without display hardware. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/gfx10: set tcp harvest for navi12Xiaojie Yuan1-3/+5
Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: add ip blocks for navi12Xiaojie Yuan1-0/+7
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/gmc10: set gart size and vm size for navi12Xiaojie Yuan1-1/+4
Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/sdma5: add placeholder for navi12 golden settingsXiaojie Yuan1-0/+11
None yet. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/sdma5: declare sdma firmwares for navi12Xiaojie Yuan1-0/+6
Declare the firmwares and load the proper ones for navi12. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/gfx10: set rlc funcs for navi12Xiaojie Yuan1-0/+1
Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12Xiaojie Yuan1-0/+1
Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/gfx10: add placeholder for navi12 golden settingsXiaojie Yuan1-0/+13
Not used yet. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/gfx10: declare cp/rlc firmwares for navi12Xiaojie Yuan1-0/+10
Set the name properly to load the right ucode. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/gfx10: add gfx config for navi12Xiaojie Yuan1-8/+2
got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE v2: squash all navi asics together because the settings are the same. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu/gfx10: set gfx cg for navi12Xiaojie Yuan1-0/+1
Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: set nbio/hdp cg for navi12Xiaojie Yuan1-0/+1
Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: initialize cg/pg flags and external rev id for navi12Xiaojie Yuan1-0/+5
don't enable any cg/pg features yet. v2: calculate external revision id from revision id so that we can differentiate navi12 A0 from A1 directly. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: use front door firmware loading for navi12Xiaojie Yuan1-0/+1
Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: set asic family and ip blocks for navi12Xiaojie Yuan1-0/+1
same with navi10 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: add gpu_info firmware for navi12Xiaojie Yuan1-0/+4
gpu_info firmare store asic configuration details. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: add navi12 asic typeXiaojie Yuan1-0/+1
Add asic type. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: initialize reg base for navi12Xiaojie Yuan4-1/+58
Set up the register offset map for navi12. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: update SDMA V4 microcode initJohn Clements1-35/+75
Removed loading duplicate instances of SDMA FW for Arcturus. We use a single image for all instances. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: extend PSP FW loading support to 8 SDMA instancesJohn Clements3-3/+41
Arcturus has 8 instances of SDMA. Update host to PSP interface to handle it. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: disable MEC2 JT context init for ArcturusJohn Clements1-5/+11
We don't need to handle it like other asics. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: update PSP CMD fail response status printJohn Clements1-2/+2
Print the response in hex with the apprpriate mask. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amdgpu: add PSP KDB loading support for ArcturusJohn Clements3-0/+29
Add support for the arcturus specific psp metadata to the amdgpu firmware and properly parse it when loading it. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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