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path: root/drivers/gpu/drm/amd/amdgpu/soc15_common.h
AgeCommit message (Expand)AuthorFilesLines
2022-04-29drm/amdgpu: add new write field for soc21Stanley.Yang1-0/+8
2022-01-26drm/amdgpu: switch to amdgpu_sriov_rreg/wregHawking Zhang1-4/+4
2021-12-29drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitionsVictor Skvortsov1-0/+5
2021-07-23drm/amdgpu: Change the imprecise function nameRoy Sun1-4/+4
2021-06-07drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10Peng Ju Zhou1-2/+2
2021-06-04drm/amdgpu: soc15 register access through RLC should only apply to sriov runtimeshaoyunl1-2/+2
2021-05-21drm/amdgpu: Indirect register access for Navi12 sriovPeng Ju Zhou1-36/+51
2021-04-09drm/amdgpu: indirect register access for nv12 sriovPeng Ju Zhou1-42/+33
2021-03-24drm/amdgpu: enable watchdog feature for SQ of aldebaranDennis Li1-0/+30
2021-03-24drm/amdgpu: add ras support for gfx of aldebaranDennis Li1-0/+18
2020-07-01drm/amdgpu: fix unused variableJames Zhu1-6/+9
2020-04-24drm/amdgpu: provide RREG32_SOC15_NO_KIQ, will be used laterMonk Liu1-0/+3
2020-03-16drm/amdgpu: revise RLCG access pathMonk Liu1-3/+2
2019-11-26drm/amdgpu: Ensure ret is always initialized when using SOC15_WAIT_ON_RREGNathan Chancellor1-0/+1
2019-08-02drm/amdgpu: cleanup vega10 SRIOV code pathMonk Liu1-2/+3
2019-05-24drm/amdgpu: move the VCN DPG mode read and write to VCNLeo Liu1-21/+0
2019-05-24drm/amdgpu: add basic func for RLC program regTrigger Huang1-1/+56
2018-12-19drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREGJames Zhu1-2/+7
2018-09-27drm/amdgpu/soc15: fix warnings in register macroAlex Deucher1-1/+1
2018-09-27drm/amdgpu:Add DPG mode read/write macroJames Zhu1-0/+20
2018-09-13drm/amdgpu:Add error message when register failed to reach expected valueJames Zhu1-0/+2
2018-05-24drm/amdgpu: Add SOC15_WAIT_ON_RREG macro defineRex Zhu1-0/+15
2017-12-14drm/amdgpu: convert nbio to use callbacks (v2)Alex Deucher1-16/+0
2017-12-08drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offsetShaoyun Liu1-5/+1
2017-12-08drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const arrayShaoyun Liu1-6/+0
2017-12-08drm/amdgpu: Use dynamic IP offset for register access on SOC15Shaoyun Liu1-26/+8
2017-07-14drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro defineShaoyun Liu1-0/+7
2017-06-15drm/amd/amdgpu: Add offset variant to SOC15 macrosTom St Denis1-0/+14
2017-04-28drm/amd/amdgpu: Introduce new read/write macros for SOC15Tom St Denis1-1/+19
2017-03-30drm/amdgpu: add common soc15 headersKen Wang1-0/+57
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