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path: root/drivers/gpu/drm/amd/amdgpu/nv.c
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2020-10-05drm/amdgpu: enable vcn3.0 for van goghThong Thai1-0/+2
Same as other VCN 3.0 asics. Signed-off-by: Thong Thai <thong.thai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amdgpu: set ip blocks for van goghHuang Rui1-0/+9
Enable ip blocks for van gogh. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2)Huang Rui1-1/+2
Van gogh only has one sdma. v2: use num_instances rather than APU flag Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amdgpu: add nv common ip block support for van goghHuang Rui1-0/+8
This patch adds common ip support for van gogh. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-01drm/amdgpu: switch to indirect reg access helperHawking Zhang1-43/+8
Switch WREG32/RREG32_PCIE to use indirect reg access helper for soc15 and onwards Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-23drm/amdgpu: fix hdp register access errorStanley.Yang1-1/+1
mmHDP_READ_CACHE_INVALIDATE register is in HDP not in NBIO Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-16drm/amdgpu: Fix consecutive DPC recovery failures.Andrey Grodzovsky1-2/+2
Cache the PCI state on boot and before each case where we might loose it. v2: Add pci_restore_state while caching the PCI state to avoid breaking PCI core logic for stuff like suspend/resume. v3: Extract pci_restore_state from amdgpu_device_cache_pci_state to avoid superflous restores during GPU resets and suspend/resumes. v4: Style fixes. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-26drm/amdgpu: use MODE1 reset for navy_flounder by defaultJiansong Chen1-0/+1
Switch default gpu reset method to MODE1 for navy_flounder. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-26drm/amdgpu: add pre_asic_init callback for naviAlex Deucher1-0/+5
Nothing to do for this family. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-15drm/amdgpu: note what type of reset we are usingAlex Deucher1-2/+4
When we reset the GPU, note what type of reset will be used. This makes debugging different reset scenarios more clear as the driver may use different reset methods depending on conditions on the system. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-08drm/amdgpu: use mode1 reset by default for sienna_cichlidLikun Gao1-3/+8
Swith default gpu reset method for sienna_cichlid to MODE1 reset. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-23drm/amdgpu: expand sienna chichlid reg access supportJohn Clements1-0/+45
Added dedicated 64bit reg read/write support Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amdgpu: enable xgmi support for sienna cichlidJohn Clements1-0/+3
set xgmi support flag suring nv ip init sequence Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable ih CG for navy_flounderJiansong Chen1-1/+2
Enable ih CG by setting the corresponding flag. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable hdp CG and LS for navy_flounderJiansong Chen1-1/+3
Enable hdp CG and LS by setting the corresponding flags. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable mc CG and LS for navy_flounderJiansong Chen1-1/+3
Enable mc CG and LS by setting the corresponding flags. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable athub/mmhub PG for navy_flounderJiansong Chen1-1/+3
Enable athub/mmhub PG by setting the corresponding flags. Actually the enablement is exercised by PMFW. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amd/display: add DC support for navy flounderBhawanpreet Lakha1-0/+4
Plumb DC support for navy flounder through. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable GFX clock gating for navy_flounderJiansong Chen1-1/+4
Enable GFX MGCG, CGCG and 3DCG for navy_flounder. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+4
Enable JPEG3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable VCN3.0 DPG for navy_flounderBoyuan Zhang1-1/+2
Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable VCN3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+2
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add vcn ip block for navy_flounderBoyuan Zhang1-0/+2
Add vcn3.0 and jpeg3.0 ip blocks for navy_flounder Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add psp block for navy_flounderJiansong Chen1-0/+5
Add psp and smu block for navy_flounder with psp firmware load type. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add smu block for navy_flounderJiansong Chen1-0/+3
Add SMU block for navy_flounder with direct firmware load type. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add virtual display support for navy_flounder.Jiansong Chen1-0/+2
Virtual display support for bring up and virtualization. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add sdma ip block for navy_flounderJiansong Chen1-0/+1
Navy_Flounder has the same sdma IP version with sienna_cichlid, and it has 2 sdma controllers. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add gfx ip block for navy_flounderJiansong Chen1-0/+1
since navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add ih ip block for navy_flounderJiansong Chen1-0/+1
navy_flounder has the same osssys IP verison with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add gmc ip block for navy_flounderJiansong Chen1-0/+1
navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add common ip block for navy_flounderJiansong Chen1-0/+3
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: initialize IP offset for navy_flounderJiansong Chen1-0/+1
since navy_flounder has the same ip offset with sienna_cichlid, follow sienna_cichlid setting for the moment. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu/soc15: add support for navy_flounderJiansong Chen1-0/+7
Add soc support. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amd/sriov skip jped ip block and close pgcg flagsJack Zhang1-1/+8
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add module parameter choose reset modeWenhui Sheng1-0/+8
Default value is auto, doesn't change original reset method logic. v2: change to use parameter reset_method v3: add warn msg if specified mode isn't supported Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable mode1 resetWenhui Sheng1-7/+12
For sienna cichlid, add mode1 reset path for sGPU. v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1 v3: split emergency restart logic to a new patch Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amdgpu: fix coding error of mmhub pg enablementLikun Gao1-3/+3
MMHUB powergating should be disabled on navi12 and enabled on sienna cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-02drm/amdgpu: request init data in virt detectionWenhui Sheng1-6/+5
Move request init data to virt detection func, so we can insert request full access between request init data and set ip blocks. Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: Enable DM block for DCN3Bhawanpreet Lakha1-0/+4
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: enable DPG mode for VCN3.0Boyuan Zhang1-0/+1
Enable DPG mode for VCN3.0 by updating related flag. V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable mmhub pgKenneth Feng1-1/+2
mmhub pg can be obvserved from PCTL_CTRL Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable athub pgKenneth Feng1-1/+2
enable athub pg and the status can be checked in ATHUB_MISC_CNTL. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOVshaoyunl1-1/+1
SMU firmware already been loaded from host, don't enable it for now. May need to re-work it if we want to enable the SMU for guest in the future. Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid.Likun Gao1-0/+1
Enable mmhub clockgating. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/amdgpu: add athub ls supportKenneth Feng1-1/+2
athub ls is bounded with hdp ls,verified. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/amdgpu: add IH cg supportKenneth Feng1-1/+2
IH cg verified Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/amdgpu: add HDP mgcg and ls supportKenneth Feng1-1/+3
add HDP mgcg and ls support and verified Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/amdgpu: fix the HDP LS/DS/SD programmingKenneth Feng1-0/+10
confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to be set for SRAM LS/DS/SD Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: open GFX clock gating for sienna_cichlidLikun Gao1-1/+4
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: enable JPEG3.0 for Sienna_CichlidLeo Liu1-0/+2
By adding JPEG HW block to Sienna_Cichlid Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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