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path: root/drivers/cxl
AgeCommit message (Expand)AuthorFilesLines
2022-07-22cxl/region: Add region creation supportBen Widawsky6-0/+274
2022-07-22cxl/mem: Enumerate port targets before adding endpointsDan Williams3-29/+47
2022-07-22cxl/hdm: Add sysfs attributes for interleave ways + granularityBen Widawsky1-0/+23
2022-07-22cxl/port: Move dport tracking to an xarrayDan Williams3-56/+47
2022-07-22cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams2-34/+30
2022-07-22cxl/port: Record parent dport when adding portsDan Williams4-20/+27
2022-07-22cxl/port: Record dport in endpoint referencesDan Williams2-17/+37
2022-07-22cxl/hdm: Add support for allocating DPA to an endpoint decoderDan Williams3-1/+259
2022-07-22cxl/hdm: Track next decoder to allocateDan Williams3-0/+18
2022-07-22cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams3-0/+39
2022-07-22cxl/hdm: Enumerate allocated DPADan Williams3-11/+149
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams3-14/+41
2022-07-21cxl/core: Define a 'struct cxl_root_decoder'Dan Williams3-13/+76
2022-07-21cxl/acpi: Track CXL resources in iomem_resourceDan Williams1-3/+141
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams4-84/+175
2022-07-20cxl/port: Read CDAT tableIra Weiny4-0/+234
2022-07-20cxl/pci: Create PCI DOE mailbox's for memory devicesIra Weiny3-0/+48
2022-07-11cxl/pmem: Delete unused nvdimm attributeDan Williams1-1/+0
2022-07-10cxl/hdm: Initialize decoder type for memory expander devicesDan Williams1-5/+11
2022-07-10cxl/port: Cache CXL host bridge dataDan Williams2-1/+19
2022-07-10tools/testing/cxl: Add partition supportDan Williams2-6/+8
2022-07-10cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem'Dan Williams4-0/+53
2022-07-10cxl/debug: Move debugfs init to cxl_core_init()Dan Williams3-12/+13
2022-07-10cxl/hdm: Require all decoders to be enumeratedBen Widawsky1-9/+3
2022-07-10cxl/mem: Convert partition-info to resourcesDan Williams4-40/+54
2022-07-10cxl: Introduce cxl_to_{ways,granularity}Dan Williams3-41/+54
2022-07-10cxl/core: Drop is_cxl_decoder()Dan Williams2-7/+0
2022-07-10cxl/core: Drop ->platform_res attribute for root decodersDan Williams4-41/+18
2022-07-10cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams3-5/+5
2022-07-10cxl/hdm: Use local hdm variableBen Widawsky1-2/+1
2022-07-09cxl/port: Keep port->uport valid for the entire life of a portDan Williams1-2/+2
2022-06-29cxl/mbox: Fix missing variable payload checks in cmd size validationVishal Verma1-2/+4
2022-06-22cxl/mbox: Use __le32 in get,set_lsa mailbox structuresAlison Schofield2-7/+7
2022-06-22cxl/core: Use is_endpoint_decoderBen Widawsky3-2/+3
2022-06-22cxl: Fix cleanup of port devices on failure to probe driver.Jonathan Cameron1-1/+6
2022-05-20cxl/port: Enable HDM Capability after validating DVSEC RangesDan Williams1-15/+152
2022-05-19cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams3-41/+25
2022-05-19cxl/port: Move endpoint HDM Decoder Capability init to port driverDan Williams2-11/+11
2022-05-19cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams3-13/+9
2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams3-88/+78
2022-05-19cxl/mem: Skip range enumeration if mem_enable clearDan Williams2-1/+3
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams5-142/+141
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams4-47/+51
2022-05-19cxl/mem: Validate port connectivity before dvsec rangesDan Williams1-16/+16
2022-05-19cxl/mem: Fix cxl_mem_probe() error exitDan Williams1-2/+4
2022-05-19cxl/pci: Drop wait_for_valid() from cxl_await_media_ready()Dan Williams1-4/+0
2022-05-19cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()Dan Williams2-20/+3
2022-05-19cxl/mem: Drop mem_enabled check from wait_for_media()Dan Williams1-4/+0
2022-04-29cxl: Drop cxl_device_lock()Dan Williams5-120/+33
2022-04-29cxl/acpi: Add root device lockdep validationDan Williams1-0/+13
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