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path: root/drivers/clocksource/timer-riscv.c
AgeCommit message (Expand)AuthorFilesLines
2023-10-11clocksource/timer-riscv: ACPI: Add timer_cannot_wakeup_cpuSunil V L1-0/+4
2023-06-01clocksource/timer-riscv: Add ACPI supportSunil V L1-0/+11
2023-06-01clocksource/timer-riscv: Refactor riscv_timer_init_dt()Sunil V L1-41/+40
2023-02-13clocksource/drivers/riscv: Patch riscv_clock_next_event() jump before first useMatt Evans1-5/+5
2023-02-13clocksource/drivers/riscv: Get rid of clocksource_arch_init() callbackLad Prabhakar1-0/+5
2023-02-13clocksource/drivers/riscv: Increase the clock source ratingSamuel Holland1-1/+1
2023-02-13clocksource/drivers/timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DTAnup Patel1-0/+10
2022-12-01Revert "clocksource/drivers/riscv: Events are stopped during CPU suspend"Conor Dooley1-1/+1
2022-08-12RISC-V: Add Sstc extension supportPalmer Dabbelt1-1/+24
2022-08-12RISC-V: Prefer sstc extension if availableAtish Patra1-1/+24
2022-07-20riscv: cpu: Add 64bit hartid support on RV64Sunil V L1-7/+8
2022-05-18clocksource/drivers/riscv: Events are stopped during CPU suspendSamuel Holland1-1/+1
2021-10-04RISC-V: KVM: Add timer functionalityAtish Patra1-0/+9
2020-08-20RISC-V: Remove CLINT related code from timer and archAnup Patel1-15/+2
2020-06-10clocksource/drivers/timer-riscv: Use per-CPU timer interruptAnup Patel1-3/+40
2020-01-05clocksource: riscv: add notrace to riscv_sched_clockZong Li1-1/+1
2019-11-14riscv: add support for MMIO access to the timer registersChristoph Hellwig1-4/+19
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-4/+4
2019-09-05riscv: don't use the rdtime(h) pseudo-instructionsChristoph Hellwig1-13/+4
2019-08-07RISC-V: Remove per cpu clocksourceAtish Patra1-4/+2
2019-03-23clocksource/drivers/riscv: Fix clocksource maskAtish Patra1-3/+2
2019-02-23clocksource/drivers/riscv: Add required checks during clock source initAtish Patra1-3/+20
2018-12-19clocksource/drivers/riscv: Change name riscv_timer to timer-riscvDaniel Lezcano1-0/+118