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2024-02-07clk: qcom: gcc-sc8180x: Set delay for Venus CLK resetsKonrad Dybcio1-3/+3
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-5-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sa8775p: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8775 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-4-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: reset: Ensure write completion on reset de/assertionKonrad Dybcio1-1/+6
Trying to toggle the resets in a rapid fashion can lead to the changes not actually arriving at the clock controller block when we expect them to. This was observed at least on SM8250. Read back the value after regmap_update_bits to ensure write completion. Fixes: b36ba30c8ac6 ("clk: qcom: Add reset controller support") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-3-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: samsung: gs101: add support for cmu_peric1André Draszik1-0/+346
CMU_PERIC1 is the clock management unit used for the peric1 block which is used for additional USI, I3C and PWM interfaces/busses. Add support for muxes, dividers and gates of cmu_peric1, except for CLK_GOUT_PERIC1_IP which isn't well described in the datasheet and which downstream also ignores (similar to cmu_peric0). Two clocks have been marked as CLK_IS_CRITICAL for the following reason: * disabling them makes it impossible to access any peric1 registers, (including those two registers). * disabling gout_peric1_lhm_axi_p_peric1_i_clk sometimes has the additional effect of making the whole system unresponsive. One clock marked as CLK_IGNORE_UNUSED needs to be kept on until we have updated the respective driver for the following reason: * gout_peric1_gpio_peric1_pclk is required by the pinctrl configuration. With this clock disabled, reconfiguring the pins (for USI/I2C, USI/UART) will hang during register access. Since pinctrl-samsung doesn't support a clock at the moment, we just keep the kernel from disabling it at boot, until we have an update for pinctrl-samsung, at which point we'll drop the flag. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-4-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-07clk: samsung: gs101: drop extra empty lineAndré Draszik1-1/+0
There is an extra empty line here which doesn't exist in any of the other cmu code blocks in this file. Drop it to align cmu_top with the rest of the file. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-2-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-06clk: qcom: reset: Commonize the de/assert functionsKonrad Dybcio1-13/+9
They do the same thing, except the last argument of the last function call differs. Commonize them. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-2-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: reset: Increase max reset delayKonrad Dybcio1-1/+1
u8 limits us to 255 microseconds of delay. Promote the delay variable to u16 to hold bigger values. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-1-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add camcc clock driver for x1e80100Rajendra Nayak3-0/+2495
Add the camcc clock driver for x1e80100 Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-10-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add TCSR clock driver for x1e80100Abel Vesa3-0/+294
The TCSR clock controller found on X1E80100 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-9-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add GPU clock driver for x1e80100Rajendra Nayak3-0/+666
Add Graphics Clock Controller (GPUCC) support for X1E80100 platform. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-8-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add dispcc clock driver for x1e80100Rajendra Nayak3-0/+1729
Add the dispcc clock driver for x1e80100. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-7-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: clk-alpha-pll: Add support for zonda ole pll configureRajendra Nayak2-0/+20
Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-6-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: microchip: mpfs: convert MSSPLL outputs to clk_dividerConor Dooley1-67/+14
After splitting the MSSPLL in two, the PLL outputs have become open-coded versions of clk_divider. Drop the custom clk ops structs, and instead use the generic clk_divider_ops. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-02-06clk: microchip: mpfs: add missing MSSPLL outputsConor Dooley1-0/+7
The MSSPLL has 4 outputs, of which only the cpu/axi/ahb clock parent is currently implemented. Add the CAN clock too, as that'll be needed by the driver for the CAN controller and uses output 3. While we are here, the other two missing clocks, used by the eMMC/SD controller and by the "user crypto". Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-02-06clk: microchip: mpfs: setup for using other mss pll outputsConor Dooley1-11/+19
Now that the MSSPLL is split, and the "postdiv" divider of the cpu/AHB/AXI bus clock is represented by its own "hw" struct, make the shifts, register offset and width a parameter of the initialisation macro, rather than using defines that only work for one of the four outputs. Configuring this at initialisaion paves the way for using the other three output clocks, where the register offset, and the bit shift within that register, will differ. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-02-06clk: microchip: mpfs: split MSSPLL in twoConor Dooley1-58/+116
The MSSPLL is really two stages - there's the PLL itself and 4 outputs, each with their own divider. The current driver models this as a single entity, outputting a single clock, used for both the CPU and AHB/AXI buses. The other 3 outputs are used for the eMMC, "user crypto" and CAN controller. Split the MSSPLL in two, as a precursor to adding support for the other 3 outputs, with the PLL itself as one "hw" clock and the output divider stage as another. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-02-06clk: renesas: r8a779h0: Add I2C clocksCong Dang1-0/+4
Add the module clocks used by the I2C Bus Interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/7a76dadbce24c81dd2bee68765a0b41beca2d565.1706790236.git.geert+renesas@glider.be
2024-02-06clk: renesas: r8a779h0: Add watchdog clockCong Dang1-0/+1
Add the module clock used by the RCLK Watchdog Timer on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f1dbf0f3f484015f2e629d78b746cf377d6f6746.1706790015.git.geert+renesas@glider.be
2024-02-06clk: renesas: r8a779h0: Add PFC/GPIO clocksCong Dang1-0/+3
Add the module clocks used by the Pin Function Controller (PFC) and General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/a7d8f4111b87decb825db5ed310de8294f90b9f9.1706266196.git.geert+renesas@glider.be
2024-02-05clk: meson: Add missing clocks to axg_clk_regmapsIgor Prusov1-0/+2
Some clocks were missing from axg_clk_regmaps, which caused kernel panic during cat /sys/kernel/debug/clk/clk_summary [ 57.349402] Unable to handle kernel NULL pointer dereference at virtual address 00000000000001fc ... [ 57.430002] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 57.436900] pc : regmap_read+0x1c/0x88 [ 57.440608] lr : clk_regmap_gate_is_enabled+0x3c/0xb0 [ 57.445611] sp : ffff800082f1b690 [ 57.448888] x29: ffff800082f1b690 x28: 0000000000000000 x27: ffff800080eb9a70 [ 57.455961] x26: 0000000000000007 x25: 0000000000000016 x24: 0000000000000000 [ 57.463033] x23: ffff800080e8b488 x22: 0000000000000015 x21: ffff00000e7e7000 [ 57.470106] x20: ffff00000400ec00 x19: 0000000000000000 x18: ffffffffffffffff [ 57.477178] x17: 0000000000000000 x16: 0000000000000000 x15: ffff0000042a3000 [ 57.484251] x14: 0000000000000000 x13: ffff0000042a2fec x12: 0000000005f5e100 [ 57.491323] x11: abcc77118461cefd x10: 0000000000000020 x9 : ffff8000805e4b24 [ 57.498396] x8 : ffff0000028063c0 x7 : ffff800082f1b710 x6 : ffff800082f1b710 [ 57.505468] x5 : 00000000ffffffd0 x4 : ffff800082f1b6e0 x3 : 0000000000001000 [ 57.512541] x2 : ffff800082f1b6e4 x1 : 000000000000012c x0 : 0000000000000000 [ 57.519615] Call trace: [ 57.522030] regmap_read+0x1c/0x88 [ 57.525393] clk_regmap_gate_is_enabled+0x3c/0xb0 [ 57.530050] clk_core_is_enabled+0x44/0x120 [ 57.534190] clk_summary_show_subtree+0x154/0x2f0 [ 57.538847] clk_summary_show_subtree+0x220/0x2f0 [ 57.543505] clk_summary_show_subtree+0x220/0x2f0 [ 57.548162] clk_summary_show_subtree+0x220/0x2f0 [ 57.552820] clk_summary_show_subtree+0x220/0x2f0 [ 57.557477] clk_summary_show_subtree+0x220/0x2f0 [ 57.562135] clk_summary_show_subtree+0x220/0x2f0 [ 57.566792] clk_summary_show_subtree+0x220/0x2f0 [ 57.571450] clk_summary_show+0x84/0xb8 [ 57.575245] seq_read_iter+0x1bc/0x4b8 [ 57.578954] seq_read+0x8c/0xd0 [ 57.582059] full_proxy_read+0x68/0xc8 [ 57.585767] vfs_read+0xb0/0x268 [ 57.588959] ksys_read+0x70/0x108 [ 57.592236] __arm64_sys_read+0x24/0x38 [ 57.596031] invoke_syscall+0x50/0x128 [ 57.599740] el0_svc_common.constprop.0+0x48/0xf8 [ 57.604397] do_el0_svc+0x28/0x40 [ 57.607675] el0_svc+0x34/0xb8 [ 57.610694] el0t_64_sync_handler+0x13c/0x158 [ 57.615006] el0t_64_sync+0x190/0x198 [ 57.618635] Code: a9bd7bfd 910003fd a90153f3 aa0003f3 (b941fc00) [ 57.624668] ---[ end trace 0000000000000000 ]--- [jbrunet: add missing Fixes tag] Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Link: https://lore.kernel.org/r/20240202172537.1.I64656c75d84284bc91e6126b50b33c502be7c42a@changeid Fixes: 14ebb3154b8f ("clk: meson: axg: add Video Clocks") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-02-01clk: samsung: exynos850: Propagate SPI IPCLK rate changeSam Protsenko1-16/+17
When SPI transfer is being prepared, the spi-s3c64xx driver will call clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK is a gate (leaf) clock, so it must propagate the rate change up the clock tree, so that corresponding DIV clocks can actually change their divider values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for all SPI instances in Exynos850 (spi_0, spi_1 and spi_2) to make it possible. This change involves next clocks: usi_spi_0: Clock Block Div range -------------------------------------------- gout_spi0_ipclk CMU_PERI - dout_peri_spi0 CMU_PERI /1..32 mout_peri_spi_user CMU_PERI - dout_peri_ip CMU_TOP /1..16 usi_cmgp0: Clock Block Div range -------------------------------------------- gout_cmgp_usi0_ipclk CMU_CMGP - dout_cmgp_usi0 CMU_CMGP /1..32 mout_cmgp_usi0 CMU_CMGP - gout_clkcmu_cmgp_bus CMU_APM - dout_apm_bus CMU_APM /1..8 usi_cmgp1: Clock Block Div range -------------------------------------------- gout_cmgp_usi1_ipclk CMU_CMGP - dout_cmgp_usi1 CMU_CMGP /1..32 mout_cmgp_usi1 CMU_CMGP - gout_clkcmu_cmgp_bus CMU_APM - dout_apm_bus CMU_APM /1..8 With input clock of 400 MHz, this scheme provides next IPCLK rate range, for each SPI block: SPI0: 781 kHz ... 400 MHz SPI1/2: 1.6 MHz ... 400 MHz Accounting for internal /4 divider in SPI blocks, and because the max SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: SPI0: 200 kHz ... 49.9 MHz SPI1/2: 400 kHz ... 49.9 MHz Which should cover all possible applications of SPI bus. Of course, setting SPI frequency to values as low as 500 kHz will also affect the common bus dividers (dout_apm_bus or dout_peri_ip), which in turn effectively lowers the rates for all leaf bus clocks derived from those dividers, like HSI2C and I3C clocks. But at least it gives the board designer a choice, whether to keep all clocks (SPI/HSI2C/I3C) at high frequencies, or make all those clocks have lower frequencies. Not propagating the rate change to those common dividers would limit this choice to "only high frequencies are allowed for SPI/HSI2C/I3C" option, making the common dividers useless. This decision follows the "Worse is better" approach, relying on the users/engineers to know the system internals when working with such low-level features, instead of trying to account for all possible use-cases. Fixes: 7dd05578198b ("clk: samsung: Introduce Exynos850 clock driver") Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240125013858.3986-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-01clk: samsung: gs101: gpio_peric0_pclk needs to be kept onAndré Draszik1-1/+1
This pclk clock is required any time we access the pinctrl registers of this block. Since pinctrl-samsung doesn't support a clock at the moment, we just keep the kernel from disabling it at boot, until we have an update for pinctrl-samsung to handle this required clock, at which point we'll be able to drop the flag again. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240130093812.1746512-2-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-31clk: renesas: r8a779g0: Fix PCIe clock nameGeert Uytterhoeven1-1/+1
Fix a typo in the name of the module clock for the second PCIe channel. Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f582067564f357e2183d3db67b217084ecb51888.1706608032.git.geert+renesas@glider.be
2024-01-31clk: renesas: cpg-mssr: Add support for R-Car V4MCong Dang5-0/+254
Initial CPG support for the R-Car V4M (R8A779H0). Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be
2024-01-31clk: renesas: rcar-gen4: Add support for FRQCRC1Geert Uytterhoeven1-2/+8
R-Car V4H and V4M have a second Frequency Control Register C. Add support for this by treating bit field offsets beyond 31 as referring to the second register. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f64d5573a92a18505619ff0ff808d50cfc2bde55.1706194617.git.geert+renesas@glider.be
2024-01-31clk: renesas: r9a07g043: Add clock and reset entries for CRUBiju Das1-0/+31
Add CRU clock and reset entries to CPG driver. CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular sequence for the CRU block hence add these clocks to r9a07g043_no_pm_mod_clks[] array and pass it as part of CPG data for RZ/G2UL SoCs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240123114415.290918-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31clk: renesas: r9a08g045: Add clock and reset support for watchdogClaudiu Beznea1-0/+3
RZ/G3S has a watchdog module accessible by the Cortex-A core. Add clock and reset support for it. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240122111115.2861835-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-30clk: qcom: gpucc-sc8280xp: Add external supply for GX gdscBjorn Andersson1-0/+1
On SA8295P and SA8540P the GFX rail is powered by a dedicated external regulator, instead of the rpmh-controlled "gfx.lvl". Define the "vdd-gfx" as the supply regulator for the GDSC, to cause the gdsc logic to look for, and control, this external power supply. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-3-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30clk: qcom: gdsc: Enable supply reglator in GPU GX handlerBjorn Andersson1-2/+10
The GX GDSC is modelled to aid the GMU in powering down the GPU in the event that the GPU crashes, so that it can be restarted again. But in the event that the power-domain is supplied through a dedicated regulator (in contrast to being a subdomin of another power-domain), something needs to turn that regulator on, both to make sure things are powered and to match the operation in gdsc_disable(). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-2-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28clk: qcom: gcc-sm8150: Add gcc video resets for sm8150Satya Priya Kakitapalli1-0/+3
Add gcc video axic, axi0 and axi1 resets for the global clock controller on sm8150. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240111-sm8150-dfs-support-v2-3-6edb44c83d3b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150Satya Priya Kakitapalli1-140/+209
QUPv3 clocks support DFS and thus register the RCGs which require support for the same. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240111-sm8150-dfs-support-v2-1-6edb44c83d3b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-25clk: rockchip: rk3568: Add PLL rate for 128MHzChris Morgan1-0/+1
Add PLL rate for 128MHz to allow the panel for the Anbernic RG-ARC series to run at 60hz. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20240123212111.202146-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-23clk: sunxi: usb: fix kernel-doc warningsRandy Dunlap1-3/+6
Move the function description comment to immediately above the function implementation, the add function parameter descriptions to prevent kernel-doc warnings: clk-usb.c:80: warning: expecting prototype for sunxi_usb_clk_setup(). Prototype was for SUNXI_USB_MAX_SIZE() instead clk-usb.c:91: warning: Function parameter or struct member 'node' not described in 'sunxi_usb_clk_setup' clk-usb.c:91: warning: Function parameter or struct member 'data' not described in 'sunxi_usb_clk_setup' clk-usb.c:91: warning: Function parameter or struct member 'lock' not described in 'sunxi_usb_clk_setup' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Emilio López <emilio@elopez.com.ar> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: <linux-clk@vger.kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Samuel Holland <samuel@sholland.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <linux-sunxi@lists.linux.dev> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20240121051858.17647-1-rdunlap@infradead.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-01-23clk: sunxi: sun9i-cpus: fix kernel-doc warningsRandy Dunlap1-3/+4
Move the function description kernel-doc comment to immediately above the function implementation, correct the function name in the comment, then add a function parameter description to prevent these kernel-doc warnings: drivers/clk/sunxi/clk-sun9i-cpus.c:25: warning: expecting prototype for sun9i_a80_cpus_clk_setup(). Prototype was for SUN9I_CPUS_MAX_PARENTS() instead clk-sun9i-cpus.c:184: warning: Function parameter or struct member 'node' not described in 'sun9i_a80_cpus_setup' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Emilio López <emilio@elopez.com.ar> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: <linux-clk@vger.kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Samuel Holland <samuel@sholland.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <linux-sunxi@lists.linux.dev> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20240121051845.17603-1-rdunlap@infradead.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-01-23clk: sunxi: a20-gmac: fix kernel-doc warningsRandy Dunlap1-10/+11
Move the function kernel-doc comment to be immediately before the function implementation, then add a function parameter description to prevent kernel-doc warnings: clk-a20-gmac.c:43: warning: expecting prototype for sun7i_a20_gmac_clk_setup(). Prototype was for SUN7I_A20_GMAC_GPIT() instead clk-a20-gmac.c:53: warning: Function parameter or struct member 'node' not described in 'sun7i_a20_gmac_clk_setup' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Emilio López <emilio@elopez.com.ar> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: <linux-clk@vger.kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Samuel Holland <samuel@sholland.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <linux-sunxi@lists.linux.dev> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20240121051837.17564-1-rdunlap@infradead.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-01-23clk: renesas: mstp: Remove obsolete clkdev registrationGeert Uytterhoeven1-13/+3
After the DT conversion of SH-Mobile and Armadillo-800-EVA display support, all devices are registered from DT, so we can remove the registration of clkdevs. Add the missing #include <linux/slab.h>, which was included implicitly through <linux/clkdev.h> before. Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e98a6e47ebecc44fa41de6d88b4ed20c6efbd177.1705931322.git.geert+renesas@glider.be
2024-01-23clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux systemKuninori Morimoto1-7/+104
Some boards might use Linux and another OS at the same time. In such case, currently, during booting, Linux will stop necessary module clocks which are not used on the Linux side, but are used by another OS. To avoid such situation, renesas-cpg-mssr tries to find status = "reserved" devices (A), and adds CLK_IGNORE_UNUSED flag to its <&cgp CPG_MOD xxx> clock (B). Table 2.4: Values for status property https://github.com/devicetree-org/devicetree-specification/releases/download/v0.4/devicetree-specification-v0.4.pdf "reserved" Indicates that the device is operational, but should not be used. Typically this is used for devices that are controlled by another software component, such as platform firmware. ex) scif5: serial@e6f30000 { ... (B) clocks = <&cpg CPG_MOD 202>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; ... (A) status = "reserved"; }; Cc: Aymeric Aillet <aymeric.aillet@iot.bzh> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/878r4ygfap.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-23clk: qcom: gcc-sdm845: Add soft dependency on rpmhpdAmit Pundir1-0/+1
With the addition of RPMh power domain to the GCC node in device tree, we noticed a significant delay in getting the UFS driver probed on AOSP which futher led to mount failures because Android do not support rootwait. So adding a soft dependency on RPMh power domain which informs modprobe to load rpmhpd module before gcc-sdm845. Cc: stable@vger.kernel.org # v5.4+ Fixes: 4b6ea15c0a11 ("arm64: dts: qcom: sdm845: Add missing RPMh power domain to GCC") Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240123062814.2555649-1-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-23clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi operationMantas Pucka1-0/+17
Without it system hangs upon wifi firmware load. It should be enabled by remoteproc/wifi driver. Bindings already exist for it, so add it based on vendor code. Signed-off-by: Mantas Pucka <mantas@8devices.com> Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-23clk: samsung: exynos850: Add PDMA clocksSam Protsenko1-1/+9
Add Peripheral DMA (PDMA) clocks in CMU_CORE controller: - PDMA_ACLK: clock for PDMA0 (regular DMA) - SPDMA_ACLK: clock for PDMA1 (secure DMA) Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240120012948.8836-4-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23clk: samsung: gs101: add support for cmu_peric0Tudor Ambarus1-0/+583
CMU_PERIC0 is the clock management unit used for the peric0 block which is used for USI and I3C. Add support for all cmu_peric0 clocks but CLK_GOUT_PERIC0_IP (not enough info in the datasheet). Few clocks are marked as critical because when either of them is disabled, the system hangs even if their clock parents are enabled. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240122114113.2582612-1-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-22clk: samsung: gs101: register cmu_misc clocks earlyPeter Griffin1-3/+9
Update cmu_misc so it is registered early, as it contains the gate which clocks the Multi Core Timer (MCT). This clock is required early in boot, otherwise exynos_mct will fail obtaining the clock. Note this wasn't previously an issue as exynos_mct wasn't enabled. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20231222165355.1462740-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-22clk: samsung: clk-gs101: comply with the new dt cmu_misc clock namesTudor Ambarus1-1/+1
The cmu_misc clock-names were renamed to just "bus" and "sss" because naming is local to the module, so cmu_misc is implied. As the bindings and the device tree have not made a release yet, comply with the renamed clocks. Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240109114908.3623645-4-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-19clk: qcom: gcc-x1e80100: Replace of_device.h with explicit includesStephen Rothwell1-1/+2
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. of_device.h isn't needed, but mod_devicetable.h and platform_device.h were implicitly included. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20231211160510.0aef871b@canb.auug.org.au [robh: Redo commit msg] Signed-off-by: Rob Herring <robh@kernel.org>
2024-01-13Merge tag 'clk-for-linus' of ↵Linus Torvalds71-637/+21379
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Only a couple new SoCs have support added this time, primarily for Qualcomm SM8650 based on the diffstat. Otherwise this is a collection of non-critical fixes and cleanups to various clk drivers and their DT bindings. Nothing is changed in the core clk framework this time, although there's a patch to fix a basic clk type initialization function. In general, this pile looks to be on the smaller side. New Drivers: - Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Mediatek MT7988 SoC clocks Updates: - Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP - Support for stm32mp25 clks - Add glitch free PLL setting support to si5351 clk driver - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 - Document bindings for i.MX93 ANATOP clock driver - Free clk_node in i.MX SCU driver for resource with different owner - Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15 - Fix the name of the fvco in i.MX pll14xx by renaming it to fout - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs - Reuse reset functionality in the Renesas RZ/G2L clock driver - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 - Cleanup variable init in Allwinner nkm module - Convert various DT bindings to YAML - A few kernel-doc fixes for Samsung SoC clock controllers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings ...
2024-01-11Merge tag 'soc-drivers-6.8' of ↵Linus Torvalds4-0/+2528
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "A new drivers/cache/ subsystem is added to contain drivers for abstracting cache flush methods on riscv and potentially others, as this is needed for handling non-coherent DMA but several SoCs require nonstandard hardware methods for it. op-tee gains support for asynchronous notification with FF-A, as well as support for a system thread for executing in secure world. The tee, reset, bus, memory and scmi subsystems have a couple of minor updates. Platform specific soc driver changes include: - Samsung Exynos gains driver support for Google GS101 (Tensor G1) across multiple subsystems - Qualcomm Snapdragon gains support for SM8650 and X1E along with added features for some other SoCs - Mediatek adds support for "Smart Voltage Scaling" on MT8186 and MT8195, and driver support for MT8188 along with some code refactoring. - Microchip Polarfire FPGA support for "Auto Update" of the FPGA bitstream - Apple M1 mailbox driver is rewritten into a SoC driver - minor updates on amlogic, mvebu, ti, zynq, imx, renesas and hisilicon" * tag 'soc-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (189 commits) memory: ti-emif-pm: Convert to platform remove callback returning void memory: ti-aemif: Convert to platform remove callback returning void memory: tegra210-emc: Convert to platform remove callback returning void memory: tegra186-emc: Convert to platform remove callback returning void memory: stm32-fmc2-ebi: Convert to platform remove callback returning void memory: exynos5422-dmc: Convert to platform remove callback returning void memory: renesas-rpc-if: Convert to platform remove callback returning void memory: omap-gpmc: Convert to platform remove callback returning void memory: mtk-smi: Convert to platform remove callback returning void memory: jz4780-nemc: Convert to platform remove callback returning void memory: fsl_ifc: Convert to platform remove callback returning void memory: fsl-corenet-cf: Convert to platform remove callback returning void memory: emif: Convert to platform remove callback returning void memory: brcmstb_memc: Convert to platform remove callback returning void memory: brcmstb_dpfe: Convert to platform remove callback returning void soc: qcom: llcc: Fix LLCC_TRP_ATTR2_CFGn offset firmware: qcom: qseecom: fix memory leaks in error paths dt-bindings: clock: google,gs101: rename CMU_TOP gate defines soc: qcom: llcc: Fix typo in kernel-doc dt-bindings: soc: qcom,aoss-qmp: document the X1E80100 Always-On Subsystem side channel ...
2024-01-09Merge branch 'clk-rs9' into clk-nextStephen Boyd1-17/+20
* clk-rs9: clk: rs9: Add support for 9FGV0841 clk: rs9: Replace model check with bitshift from chip data clk: rs9: Limit check to vendor ID in VID register dt-bindings: clk: rs9: Add 9FGV0841
2024-01-09Merge branches 'clk-zynq', 'clk-xilinx' and 'clk-stm' into clk-nextStephen Boyd13-292/+614
- Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP * clk-zynq: drivers: clk: zynqmp: update divider round rate logic drivers: clk: zynqmp: calculate closest mux rate * clk-xilinx: clocking-wizard: Add support for versal clocking wizard dt-bindings: clock: xilinx: add versal compatible * clk-stm: dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform clk: stm32mp1: use stm32mp13 reset driver clk: stm32mp1: move stm32mp1 clock driver into stm32 directory
2024-01-09Merge branches 'clk-imx', 'clk-qcom', 'clk-amlogic' and 'clk-mediatek' into ↵Stephen Boyd37-106/+20433
clk-next * clk-imx: clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() dt-bindings: clock: support i.MX93 ANATOP clock module * clk-qcom: (41 commits) clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings clk: qcom: gcc-sm8550: Mark RCGs shared where applicable clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag clk: qcom: camcc-sc8280xp: Prevent error pointer dereference clk: qcom: videocc-sm8150: Add runtime PM support clk: qcom: videocc-sm8150: Add missing PLL config property clk: qcom: videocc-sm8150: Update the videocc resets dt-bindings: clock: Update the videocc resets for sm8150 clk: qcom: rpmh: Add support for X1E80100 rpmh clocks clk: qcom: Add Global Clock controller (GCC) driver for X1E80100 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100 dt-bindings: clock: qcom: Add X1E80100 GCC clocks clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000 clk: qcom: branch: Add mem ops support for branch2 clocks ... * clk-amlogic: clk: meson: g12a: add CSI & ISP gates clocks clk: meson: g12a: add MIPI ISP clocks dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids * clk-mediatek: clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: brcm,kona-ccu: convert to YAML dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema dt-bindings: Remove alt_ref from versal
2024-01-09Merge branches 'clk-versa', 'clk-silabs', 'clk-samsung', 'clk-starfive' and ↵Stephen Boyd10-173/+221
'clk-sophgo' into clk-next - Add glitch free PLL setting support to si5351 clk driver * clk-versa: clk: versaclock3: Drop ret variable clk: versaclock3: Add missing space between ')' and '{' clk: versaclock3: Use u8 return type for get_parent() callback clk: versaclock3: Avoid unnecessary padding clk: versaclock3: Update vc3_get_div() to avoid divide by zero * clk-silabs: clk: si5351: allow PLLs to be adjusted without reset dt-bindings: clock: si5351: add PLL reset mode property dt-bindings: clock: si5351: convert to yaml * clk-samsung: clk: samsung: Improve kernel-doc comments clk: samsung: Fix kernel-doc comments * clk-starfive: clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro * clk-sophgo: dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 22:54:32 +0300