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2024-03-13Merge branches 'clk-samsung', 'clk-imx', 'clk-rockchip', 'clk-clkdev' and ↵Stephen Boyd20-290/+1502
'clk-rate-exclusive' into clk-next - Increase dev_id len for clkdev lookups * clk-samsung: (25 commits) clk: samsung: Add CPU clock support for Exynos850 clk: samsung: Pass mask to wait_until_mux_stable() clk: samsung: Keep register offsets in chip specific structure clk: samsung: Keep CPU clock chip specific data in a dedicated struct clk: samsung: Pass register layout type explicitly to CLK_CPU() clk: samsung: Pass actual CPU clock registers base to CPU_CLK() clk: samsung: Group CPU clock functions by chip clk: samsung: Use single CPU clock notifier callback for all chips clk: samsung: Reduce params count in exynos_register_cpu_clock() clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c clk: samsung: Improve clk-cpu.c style dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1 clk: samsung: gs101: add support for cmu_peric1 clk: samsung: gs101: drop extra empty line dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit clk: samsung: exynos850: Propagate SPI IPCLK rate change clk: samsung: gs101: gpio_peric0_pclk needs to be kept on clk: samsung: exynos850: Add PDMA clocks dt-bindings: clock: tesla,fsd: Fix spelling mistake clk: samsung: gs101: add support for cmu_peric0 ... * clk-imx: clk: imx: imx8mp: Fix SAI_MCLK_SEL definition clk: imx: scu: Use common error handling code in imx_clk_scu_alloc_dev() clk: imx: composite-8m: Delete two unnecessary initialisations in __imx8m_clk_hw_composite() clk: imx: composite-8m: Less function calls in __imx8m_clk_hw_composite() after error detection * clk-rockchip: clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent clk: rockchip: rk3588: use linked clock ID for GATE_LINK clk: rockchip: rk3588: fix indent clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf dt-bindings: clock: rk3588: add missing PCLK_VO1GRF dt-bindings: clock: rk3588: drop CLK_NR_CLKS clk: rockchip: rk3588: fix CLK_NR_CLKS usage clk: rockchip: rk3568: Add PLL rate for 128MHz * clk-clkdev: clkdev: Update clkdev id usage to allow for longer names * clk-rate-exclusive: clk: Add a devm variant of clk_rate_exclusive_get()
2024-03-13Merge branches 'clk-remove', 'clk-amlogic', 'clk-qcom', 'clk-parent' and ↵Stephen Boyd82-1108/+5928
'clk-microchip' into clk-next * clk-remove: clk: starfive: jh7110-vout: Convert to platform remove callback returning void clk: starfive: jh7110-isp: Convert to platform remove callback returning void clk: imx: imx8-acm: Convert to platform remove callback returning void * clk-amlogic: clk: meson: Add missing clocks to axg_clk_regmaps * clk-qcom: (62 commits) clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk' clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk' clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controller clk: qcom: drop the SC7180 Modem subsystem clock driver clk: qcom: Use qcom_branch_set_clk_en() clk: qcom: branch: Add a helper for setting the enable bit clk: qcom: dispcc-sm8250: Make clk_init_data and pll_vco const clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks clk: qcom: gcc-msm8953: add more resets clk: qcom: videocc-*: switch to module_platform_driver ... * clk-parent: clk: Fix clk_core_get NULL dereference * clk-microchip: clk: microchip: mpfs: convert MSSPLL outputs to clk_divider clk: microchip: mpfs: add missing MSSPLL outputs clk: microchip: mpfs: setup for using other mss pll outputs clk: microchip: mpfs: split MSSPLL in two dt-bindings: can: mpfs: add missing required clock dt-bindings: clock: mpfs: add more MSSPLL output definitions
2024-03-13Merge branches 'clk-aspeed', 'clk-keystone', 'clk-mobileye' and ↵Stephen Boyd6-34/+123
'clk-allwinner' into clk-next * clk-aspeed: clk: ast2600: Add FSI parent clock with correct rate dt-bindings: clock: ast2600: Add FSI clock * clk-keystone: clk: keystone: sci-clk: Adding support for non contiguous clocks * clk-mobileye: dt-bindings: reset: mobileye,eyeq5-reset: add bindings dt-bindings: clock: mobileye,eyeq5-clk: add bindings clk: fixed-factor: add fwname-based constructor functions clk: fixed-factor: add optional accuracy support * clk-allwinner: clk: sunxi: usb: fix kernel-doc warnings clk: sunxi: sun9i-cpus: fix kernel-doc warnings clk: sunxi: a20-gmac: fix kernel-doc warnings
2024-03-13Merge branches 'clk-renesas', 'clk-cleanup', 'clk-hisilicon', 'clk-mediatek' ↵Stephen Boyd15-28/+89
and 'clk-bulk' into clk-next - Add a devm_clk_bulk_get_all_enable() API to get and enable all clks for a device - Fix some static checker errors in the hisilicon clk driver * clk-renesas: (25 commits) clk: renesas: r8a779h0: Add RPC-IF clock clk: renesas: r8a779h0: Add SYS-DMAC clocks clk: renesas: r8a779h0: Add SDHI clock clk: renesas: r8a779h0: Add EtherAVB clocks clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux clk: renesas: r8a779f0: Correct PFC/GPIO parent clock clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks clk: renesas: r8a779h0: Add I2C clocks clk: renesas: r8a779h0: Add watchdog clock clk: renesas: r8a779h0: Add PFC/GPIO clocks clk: renesas: r8a779g0: Fix PCIe clock name clk: renesas: cpg-mssr: Add support for R-Car V4M clk: renesas: rcar-gen4: Add support for FRQCRC1 clk: renesas: r9a07g043: Add clock and reset entries for CRU clk: renesas: r9a08g045: Add clock and reset support for watchdog dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support dt-bindings: power: Add r8a779h0 SYSC power domain definitions dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support ... * clk-cleanup: clk: zynq: Prevent null pointer dereference caused by kmalloc failure clk: fractional-divider: Use bit operations consistently clk: fractional-divider: Move mask calculations out of lock clk: ti: dpll3xxx: use correct function names in kernel-doc clk: clocking-wizard: Remove redundant initialization of pointer div_addr clk: keystone: sci-clk: match func name comment to actual clk: cdce925: Remove redundant assignment to variable 'rate' MAINTAINERS: drop Sekhar Nori * clk-hisilicon: clk: hisilicon: Use devm_kcalloc() instead of devm_kzalloc() clk: hisilicon: hi3559a: Fix an erroneous devm_kfree() clk: hisilicon: hi3519: Release the correct number of gates in hi3519_clk_unregister() * clk-mediatek: clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe() clk: mediatek: add infracfg reset controller for mt7988 dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock dt-bindings: clock: mediatek: convert hifsys to the json-schema clock clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF clk: mediatek: mt7622-apmixedsys: Fix an error handling path in clk_mt8135_apmixed_probe() clk: mediatek: mt8135: Fix an error handling path in clk_mt8135_apmixed_probe() * clk-bulk: clk: Provide managed helper to get and enable bulk clocks
2024-03-12clk: x86: Move clk-pmc-atom register defines to ↵Hans de Goede1-12/+1
include/linux/platform_data/x86/pmc_atom.h Move the register defines for the Atom (Bay Trail, Cherry Trail) PMC clocks to include/linux/platform_data/x86/pmc_atom.h. This is a preparation patch to extend the S0i3 readiness checks in drivers/platform/x86/pmc_atom.c with checking that the PMC clocks are off on suspend entry. Note these are added to include/linux/platform_data/x86/pmc_atom.h rather then to include/linux/platform_data/x86/clk-pmc-atom.h because the former already has all the other Atom PMC register defines. Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20240305105915.76242-2-hdegoede@redhat.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
2024-03-09clk: zynq: Prevent null pointer dereference caused by kmalloc failureDuoming Zhou1-5/+3
The kmalloc() in zynq_clk_setup() will return null if the physical memory has run out. As a result, if we use snprintf() to write data to the null address, the null pointer dereference bug will happen. This patch uses a stack variable to replace the kmalloc(). Fixes: 0ee52b157b8e ("clk: zynq: Add clock controller driver") Suggested-by: Michal Simek <michal.simek@amd.com> Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Duoming Zhou <duoming@zju.edu.cn> Link: https://lore.kernel.org/r/20240301084437.16084-1-duoming@zju.edu.cn Acked-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-09clk: fractional-divider: Use bit operations consistentlyAndy Shevchenko1-4/+4
Use BIT() where makes sense. This alings usage of bit operations in the same pieces of code. Moreover, strictly speaking by the letter of the C standard, left shift of 1 by 31 bits is UB (undefined behaviour), switching to BIT() addresses that as well. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240303120732.240355-1-andy.shevchenko@gmail.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-09clk: fractional-divider: Move mask calculations out of lockAndy Shevchenko1-3/+3
There is no need to calculate masks under the lock taken. Move them out of it. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20240303121410.240761-1-andy.shevchenko@gmail.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-09clk: Fix clk_core_get NULL dereferenceBryan O'Donoghue1-0/+3
It is possible for clk_core_get to dereference a NULL in the following sequence: clk_core_get() of_clk_get_hw_from_clkspec() __of_clk_get_hw_from_provider() __clk_get_hw() __clk_get_hw() can return NULL which is dereferenced by clk_core_get() at hw->core. Prior to commit dde4eff47c82 ("clk: Look for parents with clkdev based clk_lookups") the check IS_ERR_OR_NULL() was performed which would have caught the NULL. Reading the description of this function it talks about returning NULL but that cannot be so at the moment. Update the function to check for hw before dereferencing it and return NULL if hw is NULL. Fixes: dde4eff47c82 ("clk: Look for parents with clkdev based clk_lookups") Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240302-linux-next-24-03-01-simple-clock-fixes-v1-1-25f348a5982b@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-09clk: starfive: jh7110-vout: Convert to platform remove callback returning voidUwe Kleine-König1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/90054b8b2e118bc04ec37e044d0ac518bb177cf4.1709721042.git.u.kleine-koenig@pengutronix.de Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-09clk: starfive: jh7110-isp: Convert to platform remove callback returning voidUwe Kleine-König1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/312ec7052c4e327c0b365e167a8e86b406cb7dfa.1709721042.git.u.kleine-koenig@pengutronix.de Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-09clk: imx: imx8-acm: Convert to platform remove callback returning voidUwe Kleine-König1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/ba373ce7341518216a4940e76ce61d759b912b3d.1709721042.git.u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-04Merge tag 'omap-for-v6.9/dt-warnings-signed' of ↵Arnd Bergmann7-37/+70
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/late Update TI clksel clocks to use reg Updates for TI clksel clocks to use the standard reg property instead of the non-standard ti,bit-shift legacy property. There are still lots of TI composite clock related devicetree warnings for missing bindings, and overlapping reg properties. We have grouped some of the TI composite clocks under the clksel clock node, but did not consider the reg property issue. Let's update the existing users before we continue grouping more of the composite clocks. * tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift clk: ti: Improve clksel clock bit parsing for reg property clk: ti: Handle possible address in the node name Link: https://lore.kernel.org/r/pull-1709102378-94138@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-03-04Merge tag 'v6.9-rockchip-dts64-2' of ↵Arnd Bergmann3-1/+23
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt Initial support for the rk3568 Qnap TS433 NAS, the rk3588-based Tiger SoM from Theobroma-Systems and the rk3588-based Toybrick TB-RK3588X. Some fixes to conform to dt-bindings for i2s (rk3588, rk356x) and rk356x video-decoder (missing interrupt-names). Correcting the vendor in the compatible for OrangePi RK3399 and BananaPi R2 Pro (discussed with DT-maintainers beforehand of course). The VO1-GRF syscon needs its clock to work, and that clock also needed to be actually exported forst, so we're sharing a branch with the Rockchip clock-tree (that already got merged into the main clock-tree for 6.9) for this small shared code. And as another step on the long road to graphics output on rk3588, 6.9 will get the hdmi-phy via the phy-tree, so here the dts node is added. * tag 'v6.9-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Fix name for UART pin header on qnap-ts433 arm64: dts: rockchip: Add basic support for QNAP TS-433 dt-bindings: arm: rockchip: Add QNAP TS-433 arm64: dts: rockchip: add Haikou baseboard with RK3588-Q7 SoM arm64: dts: rockchip: add RK3588-Q7 (Tiger) SoM dt-bindings: arm: rockchip: Add Theobroma-Systems RK3588 Q7 with baseboard arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s arm64: dts: rockchip: fix reset-names for rk356x i2s2 controller arm64: dts: rockchip: add missing interrupt-names for rk356x vdpu arm64: dts: rockchip: add clock to vo1-grf syscon on rk3588 dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X arm64: dts: rockchip: Add devicetree support for TB-RK3588X board arm64: dts: rockchip: adjust vendor on orangepi rk3399 board arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board dt-bindings: arm: rockchip: Correct vendor for Banana Pi R2 Pro dt-bindings: arm: rockchip: Correct vendor for Orange Pi RK3399 board arm64: dts: rockchip: Add HDMI0 PHY to rk3588 dt-bindings: clock: rk3588: add missing PCLK_VO1GRF dt-bindings: clock: rk3588: drop CLK_NR_CLKS clk: rockchip: rk3588: fix CLK_NR_CLKS usage Link: https://lore.kernel.org/r/3695004.ElGaqSPkdT@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-03-04clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES resetGabor Juhos1-1/+1
The current register offset used for the GCC_UBI0_AXI_ARES reset seems wrong. Or at least, the downstream driver uses [1] the same offset which is used for other the GCC_UBI0_*_ARES resets. Change the code to use the same offset used in the downstream driver and also specify the reset bit explicitly to use the same format as the followup entries. 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L3773 Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20240225-gcc-ipq5018-register-fixes-v1-3-3c191404d9f0@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-04clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk'Gabor Juhos1-1/+1
The following table shows the values of the 'halt_reg' and the 'enable_reg' fields from the pcie clocks defined in the current driver: clock halt_reg enable_reg gcc_pcie0_ahb_clk 0x75010 0x75010 gcc_pcie0_aux_clk 0x75014 0x75014 gcc_pcie0_axi_m_clk 0x75008 0x75008 gcc_pcie0_axi_s_bridge_clk 0x75048 0x75048 gcc_pcie0_axi_s_clk 0x7500c 0x7500c gcc_pcie0_pipe_clk 0x75018 0x75018 gcc_pcie1_ahb_clk 0x76010 0x76010 gcc_pcie1_aux_clk 0x76014 0x76014 gcc_pcie1_axi_m_clk 0x76008 0x76008 gcc_pcie1_axi_s_bridge_clk 0x76048 0x76048 gcc_pcie1_axi_s_clk 0x7600c 0x7600c gcc_pcie1_pipe_clk 8* 0x76018 Based on the table, it is quite likely that the pcie0 and the pci1 clocks are using the same register layout, however it seems that the value of the 'halt_reg' field in the 'gcc_pcie1_pipe_clk' clock is wrong. In the downstream driver [1], the same '0x76018' value is used for both the 'halt_reg' and for the 'enable_reg' fields of the 'gcc_pcie1_pipe_clk' clock. Update the current driver to use the same value used downstream as probably that is the correct value. 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L2316 Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20240225-gcc-ipq5018-register-fixes-v1-2-3c191404d9f0@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-04clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk'Gabor Juhos1-1/+1
The value of the 'enable_reg' field in the 'gcc_gmac0_sys_clk' clock definition seems wrong as it is greater than the 'max_register' value defined in the regmap configuration. Additionally, all other gmac specific branch clock definitions within the driver uses the same value both for the 'enable_reg' and for the 'halt_reg' fields. Due to the lack of documentation the correct value is not known. Looking into the downstream driver does not help either, as that uses the same (presumably wrong) value [1]. Nevertheless, change the 'enable_reg' field of 'gcc_gmac0_sys_clk' to use the value from the 'halt_reg' field so it follows the pattern used in other gmac clock definitions. The change is based on the assumption that the register layout of this clock is the same as the other gmac clocks. 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L1889 Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20240225-gcc-ipq5018-register-fixes-v1-1-3c191404d9f0@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-02clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camccBryan O'Donoghue1-0/+1
The desired DT pattern for clock indexing is the following: clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; In order to facilitate that indexing structure we need to have DT_IFACE enum defined. Fixes: 76126a5129b5 ("clk: qcom: Add camcc clock driver for x1e80100") Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240302-linux-next-24-03-01-simple-clock-fixes-v1-2-25f348a5982b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-02clk: qcom: mmcc-msm8974: fix terminating of frequency table arraysGabor Juhos1-0/+2
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-7-074334f0905c@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-02clk: qcom: mmcc-apq8084: fix terminating of frequency table arraysGabor Juhos1-0/+2
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: 2b46cd23a5a2 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-6-074334f0905c@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-02clk: qcom: camcc-sc8280xp: fix terminating of frequency table arraysGabor Juhos1-0/+21
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: ff93872a9c61 ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-5-074334f0905c@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-02clk: qcom: gcc-ipq9574: fix terminating of frequency table arraysGabor Juhos1-0/+1
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-4-074334f0905c@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-02clk: qcom: gcc-ipq8074: fix terminating of frequency table arraysGabor Juhos1-0/+2
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: 9607f6224b39 ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-3-074334f0905c@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-02clk: qcom: gcc-ipq6018: fix terminating of frequency table arraysGabor Juhos1-0/+2
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-2-074334f0905c@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-02clk: qcom: gcc-ipq5018: fix terminating of frequency table arraysGabor Juhos1-0/+3
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-1-074334f0905c@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-29clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in ↵Markus Elfring1-2/+3
clk_mt8173_apmixed_probe() Add a label so that a bit of exception handling can be better reused at the end of this function implementation. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Link: https://lore.kernel.org/r/6a64e7b3-b1ce-46c4-9c85-89f731aee592@web.de Reviewed-by: AngeloGiaocchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-29clk: Add a devm variant of clk_rate_exclusive_get()Uwe Kleine-König1-0/+19
This allows to simplify drivers that use clk_rate_exclusive_get() in their probe routine as calling clk_rate_exclusive_put() is cared for automatically. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20240104225512.1124519-2-u.kleine-koenig@pengutronix.de Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-29clk: ti: dpll3xxx: use correct function names in kernel-docRandy Dunlap1-2/+2
Use function names that match the implementation in kernel-doc comments to avoid kernel-doc warnings: dpll3xxx.c:938: warning: expecting prototype for omap3_non_core_dpll_save_context(). Prototype was for omap3_noncore_dpll_save_context() instead dpll3xxx.c:967: warning: expecting prototype for omap3_core_dpll_restore_context(). Prototype was for omap3_noncore_dpll_restore_context() instead Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Tero Kristo <kristo@kernel.org> Cc: linux-omap@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20240115054739.4988-1-rdunlap@infradead.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-29clk: clocking-wizard: Remove redundant initialization of pointer div_addrColin Ian King1-1/+1
The pointer div_addr is being assigned a value that is never used, it is being re-assigned a different value near the end of the function where it is being read in the next statement. The initialization is redundant and can be removed. Cleans up clang scan build warning: drivers/clk/xilinx/clk-xlnx-clock-wizard.c:501:16: warning: Value stored to 'div_addr' during its initialization is never read [deadcode.DeadStores] Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20240223134347.3908301-1-colin.i.king@gmail.com Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-29clkdev: Update clkdev id usage to allow for longer namesMichael J. Ruhl1-1/+1
clkdev DEV ID information is limited to an array of 20 bytes (MAX_DEV_ID). It is possible that the ID could be longer than that. If so, the lookup will fail because the "real ID" will not match the copied value. For instance, generating a device name for the I2C Designware module using the PCI ID can result in a name of: i2c_designware.39424 clkdev_create() will store: i2c_designware.3942 The stored name is one off and will not match correctly during probe. Increase the size of the ID to allow for a longer name. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Link: https://lore.kernel.org/r/20240223202556.2194021-1-michael.j.ruhl@intel.com Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-02-28clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parentOndrej Jirman1-3/+3
Otherwise when when clk_i2s0 muxes to clk_i2s0_div which requires setting high divider value on clk_i2s0_div, and then muxes back to clk_i2s0_frac, clk_i2s0_frac would have no way to change the clk_i2s0_div's divider ratio back to 1 so that it can satisfy the condition for m/n > 20 for fractional division to work correctly. Bug is reproducible by playing 44.1k audio, then 48k audio, and then 44.1k audio again. This results in clk_i2s0_div being set to 49 and clk_i2s0_frac not being able to cope with such a low input clock rate and audio playing extremely slowly. The identical issue is on i2s1 and i2s2 clocks, too. Signed-off-by: Ondrej Jirman <megi@xff.cz> Link: https://lore.kernel.org/r/20240217193439.1762213-1-megi@xff.cz Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-28clk: rockchip: rk3588: use linked clock ID for GATE_LINKSebastian Reichel1-23/+23
In preparation for properly supporting GATE_LINK switch the unused linked clock argument from the clock's name to its ID. This allows easy and fast lookup of the 'struct clk'. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-28clk: rockchip: rk3588: fix indentSebastian Reichel1-1/+1
pclk_mailbox2 is the only RK3588 clock indented with one tab instead of two tabs. Let's fix this. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-28clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grfSebastian Reichel1-6/+4
Currently pclk_vo1grf is not exposed, but it should be referenced from the vo1_grf syscon, which needs it enabled. That syscon is required for HDMI RX and TX functionality among other things. Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates and need the VO's hclk enabled in addition to their parent clock. No Fixes tag has been added, since the logic requiring these clocks is not yet upstream anyways. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-28Merge branch 'v6.9-shared/clkids' into v6.9-clk/nextHeiko Stuebner3-1/+23
2024-02-27clk: rockchip: rk3588: fix CLK_NR_CLKS usageSebastian Reichel3-1/+23
CLK_NR_CLKS is not part of the DT bindings and needs to be removed from it, just like it recently happened for other platforms. This takes care of it by introducing a new function identifying the maximum used clock ID at runtime. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-26clk: ti: Improve clksel clock bit parsing for reg propertyTony Lindgren7-33/+60
Because of legacy reasons, the TI clksel composite clocks can have overlapping reg properties, and use a custom ti,bit-shift property. For the clksel clocks we can start using of the standard reg property instead of the custom ti,bit-shift property. To do this, let's add a ti_clk_get_legacy_bit_shift() helper, and make ti_clk_get_reg_addr() populate the clock bit offset. This makes it possible to update the devicetree files to use the reg property one clock at a time. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2024-02-26clk: ti: Handle possible address in the node nameTony Lindgren1-4/+10
In order to use #address-cells = <1> and start making use of the standard reg property, let's prepare things to ignore the possible address in the clock node name. Unless the clock-output-names property is used, the legacy clocks still fall back to matching the clock data based on the node name. We use cleanup.h to simplify the return path for freeing tmp. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2024-02-26clk: imx: imx8mp: Fix SAI_MCLK_SEL definitionShengjiu Wang1-3/+8
There is SAI1, SAI2, SAI3, SAI5, SAI6, SAI7 existing in this block control, the order is discontinuous. The definition of SAI_MCLK_SEL(n) is not match with the usage of CLK_SAIn(n). So define SAI##n##_MCLK_SEL separately to fix the issue. Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/1708683351-8504-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-02-26clk: imx: scu: Use common error handling code in imx_clk_scu_alloc_dev()Markus Elfring1-12/+10
Add a jump target so that a bit of exception handling can be better reused at the end of this function. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/01446ce9-c0e8-4467-8b2d-fd736bc5b8e4@web.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-02-26clk: imx: composite-8m: Delete two unnecessary initialisations in ↵Markus Elfring1-2/+2
__imx8m_clk_hw_composite() Two local variables will eventually be set to appropriate pointers a bit later. Thus omit the explicit initialisation at the beginning. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/6604590e-d0f7-4798-a1b9-b2f474f3a642@web.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-02-26clk: imx: composite-8m: Less function calls in __imx8m_clk_hw_composite() ↵Markus Elfring1-5/+7
after error detection The function “kfree” was called in up to three cases by the function “__imx8m_clk_hw_composite” during error handling even if the passed variables contained a null pointer. Adjust jump targets according to the Linux coding style convention. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/147ca1e6-69f3-4586-b5b3-b69f9574a862@web.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-02-25clk: samsung: Add CPU clock support for Exynos850Sam Protsenko2-0/+181
Implement CPU clock control for Exynos850 SoC. It follows the same procedure which is already implemented for other SoCs in clk-cpu.c: 1. Set the correct rate for the alternate parent (if needed) before switching to use it as the CPU clock 2. Switch to the alternate parent, so the CPU continues to get clocked while the PLL is being re-configured 3. Adjust the dividers for the CPU related buses (ACLK, ATCLK, etc) 4. Re-configure the PLL for the new CPU clock rate. It's done automatically, as the CPU clock rate change propagates to the PLL clock, because the CPU clock has CLK_SET_RATE_PARENT flag set in exynos_register_cpu_clock() 5. Once the PLL is locked, set it back as the CPU clock source 6. Set alternate parent clock rate back to max speed As in already existing clk-cpu.c code, the divider and mux clocks are configured in a low-level fashion (using direct register access instead of CCF API), to avoid affecting how DIV and MUX clock flags are declared in the actual clock driver (clk-exynos850.c). No functional change. This patch adds support for Exynos850 CPU clock, but doesn't enable it per se. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-13-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Pass mask to wait_until_mux_stable()Sam Protsenko1-7/+7
Make it possible to use wait_until_mux_stable() for MUX registers where the mask is different from MUX_MASK (e.g. in upcoming CPU clock implementation for Exynos850). No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-12-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Keep register offsets in chip specific structureSam Protsenko1-70/+86
Abstract CPU clock registers by keeping their offsets in a dedicated chip specific structure to accommodate for oncoming Exynos850 support, which has different offsets for cluster 0 and cluster 1. This rework also makes it possible to use exynos_set_safe_div() for all chips, so exynos5433_set_safe_div() is removed here to reduce the code duplication. The ".regs" field has to be (void *) as different Exynos chips can have very different register layout, so this way it's possible for ".regs" to point to different structures, each representing its own chip's layout. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-11-semen.protsenko@linaro.org [krzysztof: drop redundant const for regs in exynos_cpuclk_chip] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Keep CPU clock chip specific data in a dedicated structSam Protsenko1-14/+26
Keep chip specific data in the data structure, don't mix it with code. It makes it easier to add more chip specific data further. Having all chip specific data in the table eliminates possible code bloat when adding more rate handlers for new chips, and also makes it possible to keep some other chip related data in that array. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-10-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Pass register layout type explicitly to CLK_CPU()Sam Protsenko8-17/+29
Use a dedicated enum field to explicitly specify which register layout should be used for the CPU clock, instead of passing it as a bit flag. This way it would be possible to keep the chip-specific data in some array, where each chip structure could be accessed by its corresponding layout index. It prepares clk-cpu.c for adding new chips support, which might have different data for different CPU clusters. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-9-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Pass actual CPU clock registers base to CPU_CLK()Sam Protsenko6-39/+40
The documentation for struct exynos_cpuclk says .ctrl_base field should contain the controller base address. There are two different problems with that: 1. All Exynos clock drivers are actually passing CPU_SRC register offset via CPU_CLK() macro, which in turn gets assigned to mentioned .ctrl_base field. Because CPU_SRC register usually already has 0x200 offset from controller's base, all other register offsets in clk-cpu.c (like DIVs and MUXes) are specified as offsets from CPU_SRC offset, and not from controller's base. That makes things confusing and inconsistent with register offsets provided in Exynos clock drivers, also breaking the contract for .ctrl_base field as described in struct exynos_cpuclk doc. 2. Furthermore, some Exynos chips have an additional offset for the start of CPU clock registers block (inside of the CMU). There might be different reasons for that, e.g.: - The CMU contains clocks for two different CPUs (like in Exynos5420) - The CMU contains also non-CPU clocks as well (like in Exynos4) - The CPU CMU exists as a dedicated hardware block in the SoC layout, but is modelled as a part of bigger CMU in the driver (like in case of Exynos3250) That means the .ctrl_base field is actually not a controller's base, but instead it's a start address of the CPU clock registers inside of the CMU. Rework all register offsets in clk-cpu.c to be actual offsets from the CPU clock register block start, and fix offsets provided to CPU_CLK() macro in all Exynos clock drivers. Also clarify the .ctrl_base field documentation and rename it to just .base, because it doesn't really contain the CMU base. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Group CPU clock functions by chipSam Protsenko1-53/+61
clk-cpu.c is going to get messy as new chips support is added. Restructure the code by pulling related functions and definitions together, grouping those by their relation to a particular chip or other categories, to simplify the code navigation. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-7-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25clk: samsung: Use single CPU clock notifier callback for all chipsSam Protsenko1-35/+28
Reduce the code duplication by making all chips use a single version of exynos_cpuclk_notifier_cb() function. That will prevent the code bloat when adding new chips support too. Also don't pass base address to pre/post rate change functions, as it can be easily derived from already passed cpuclk param. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-6-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 13:31:31 +0300