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2024-04-16clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rateFrank Oltmanns2-0/+23
The Allwinner A64 manual lists the following constraints for the PLL-MIPI clock: - M/N <= 3 - (PLL_VIDEO0)/M >= 24MHz The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for these constraints. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-3-46fc80c83637@oltmanns.dev Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-04-16clk: sunxi-ng: a64: Set minimum and maximum rate for PLL-MIPIFrank Oltmanns1-0/+2
When the Allwinner A64's TCON0 searches the ideal rate for the connected panel, it may happen that it requests a rate from its parent PLL-MIPI which PLL-MIPI does not support. This happens for example on the Olimex TERES-I laptop where TCON0 requests PLL-MIPI to change to a rate of several GHz which causes the panel to stay blank. It also happens on the pinephone where a rate of less than 500 MHz is requested which causes instabilities on some phones. Set the minimum and maximum rate of Allwinner A64's PLL-MIPI according to the Allwinner User Manual. Fixes: ca1170b69968 ("clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux") Reported-by: Diego Roversi <diegor@tiscali.it> Closes: https://groups.google.com/g/linux-sunxi/c/Rh-Uqqa66bw Tested-by: Diego Roversi <diegor@tiscali.it> Cc: stable@vger.kernel.org Reviewed-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-2-46fc80c83637@oltmanns.dev Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-04-16clk: sunxi-ng: common: Support minimum and maximum rateFrank Oltmanns2-0/+22
The Allwinner SoC's typically have an upper and lower limit for their clocks' rates. Up until now, support for that has been implemented separately for each clock type. Implement that functionality in the sunxi-ng's common part making use of the CCF rate liming capabilities, so that it is available for all clock types. Suggested-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Cc: stable@vger.kernel.org Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-1-46fc80c83637@oltmanns.dev Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-04-16clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate changeJernej Skrabec1-2/+17
While PLL CPUX clock rate change when CPU is running from it works in vast majority of cases, now and then it causes instability. This leads to system crashes and other undefined behaviour. After a lot of testing (30+ hours) while also doing a lot of frequency switches, we can't observe any instability issues anymore when doing reparenting to stable clock like 24 MHz oscillator. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Reported-by: Chad Wagner <wagnerch42@gmail.com> Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/ Tested-by: Chad Wagner <wagnerch42@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20231013181712.2128037-1-jernej.skrabec@gmail.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-04-12clk: stm32: introduce clocks for STM32MP257 platformGabriel Fernandez6-15/+2646
This driver is intended for the STM32MP25 clock family and utilizes the stm32-core API, similar to the stm32mp13 clock driver. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20240411092453.243633-4-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-12clk: stm32mp13: use platform device APIsGabriel Fernandez2-73/+10
Convert devm_platform_ioremap_resource() and remove unnecessary dependency check with SCMI clock driver. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20240411092453.243633-2-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-12clk: sophgo: Make synthesizer struct staticInochi Amaoto1-6/+6
Let all synthesizer structs are static to make the compiler happy. Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://lore.kernel.org/r/IA1PR20MB49531E437735A71A163694AEBB052@IA1PR20MB4953.namprd20.prod.outlook.com Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202404120548.y9dZIi0e-lkp@intel.com/ Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: clk-loongson2: Add Loongson-2K2000 clock supportBinbin Zhou1-0/+72
The Loongson-2K2000 and Loongson-2K1000 clock is similar, we add its support by different configurations. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://lore.kernel.org/r/8b0b5851783acf8ebe13b50391d15b58cc181613.1712731524.git.zhoubinbin@loongson.cn Acked-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: clk-loongson2: Add Loongson-2K0500 clock supportBinbin Zhou1-0/+22
The Loongson-2K0500 and Loongson-2K1000 clock is similar, we add its support by different configurations. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://lore.kernel.org/r/f767a1783dc590fcd31ff7d4459df2cf80196de1.1712731524.git.zhoubinbin@loongson.cn Acked-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: clk-loongson2: Refactor driver for adding new platformsBinbin Zhou1-260/+198
The driver only supported loongson-2K1000 at first, but the clock structure of loongson-2K0500 and loongson-2K2000 are actually similar, and I tried to refactor the whole driver to adjust to the addition of the new platform. Briefly, I have divided all clocks into three categories according to their properties and their parent clocks: Independent PLLs, clocks based on frequency scales, and clock dividers. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://lore.kernel.org/r/fb020d1ca19e6f4cdcc95c87b2748869ca76b8ec.1712731524.git.zhoubinbin@loongson.cn Acked-by: Huacai Chen <chenhuacai@loongson.cn> [sboyd@kernel.org: Drop clk.h include] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: sophgo: Add clock support for SG2000 SoCInochi Amaoto1-0/+15
Add init code for SG2000 SoC. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://github.com/sophgo/sophgo-doc/releases/tag/sg2000-datasheet-v1.0-alpha Link: https://lore.kernel.org/r/IA1PR20MB49537156E71B64483F15C0F2BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: sophgo: Add clock support for CV1810 SoCInochi Amaoto2-0/+196
Add clock definition and init code for CV1810 SoC. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV180X-Clock-v1.xlsx Link: https://lore.kernel.org/r/IA1PR20MB495357FB5EEA1623DAB08C94BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: sophgo: Add clock support for CV1800 SoCInochi Amaoto12-0/+3302
Add clock definition and driver code for CV1800 SoC. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV180X-Clock-v1.xlsx Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf Link: https://lore.kernel.org/r/IA1PR20MB49534F37F802CAF117364D66BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: mediatek: pllfh: Don't log error for missing fhctl nodeNícolas F. R. A. Prado1-1/+1
Support for fhctl clocks in apmixedsys was introduced at a later point and to this moment only one mt6795 based platform has a fhctl DT node present. Therefore the fhctl support in apmixedsys should be seen as optional and not cause an error when it is missing. Change the message's log level to warning. The warning level is chosen so that it will still alert the fact that fhctl support might be unintentionally missing, but without implying that this is necessarily an issue. Even if the FHCTL DT nodes are added to all current platforms moving forward, since those changes won't be backported, this ensures stable kernel releases won't have live with this error. Fixes: d7964de8a8ea ("clk: mediatek: Add new clock driver to handle FHCTL hardware") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20240308-mtk-fhctl-no-node-error-v1-1-51e446eb149a@collabora.com Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe portDaniel Golle1-1/+1
Due to what seems to be an undocumented oddity in MediaTek's MT7988 SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled. This currently leads to PCIe port 2 not working in Linux. Reflect the apparent relationship in the clk driver to make sure PCIe port 2 of the MT7988 SoC works. Fixes: 4b4719437d85f ("clk: mediatek: add drivers for MT7988 SoC") Suggested-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/1da2506a51f970706bf4ec9509dd04e0471065e5.1710367453.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: mediatek: Do a runtime PM get on controllers during probePin-yen Lin1-0/+15
mt8183-mfgcfg has a mutual dependency with genpd during the probing stage, which leads to a deadlock in the following call stack: CPU0: genpd_lock --> clk_prepare_lock genpd_power_off_work_fn() genpd_lock() generic_pm_domain::power_off() clk_unprepare() clk_prepare_lock() CPU1: clk_prepare_lock --> genpd_lock clk_register() __clk_core_init() clk_prepare_lock() clk_pm_runtime_get() genpd_lock() Do a runtime PM get at the probe function to make sure clk_register() won't acquire the genpd lock. Instead of only modifying mt8183-mfgcfg, do this on all mediatek clock controller probings because we don't believe this would cause any regression. Verified on MT8183 and MT8192 Chromebooks. Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support") Signed-off-by: Pin-yen Lin <treapking@chromium.org> Link: https://lore.kernel.org/r/20240312115249.3341654-1-treapking@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: en7523: Add EN7581 supportLorenzo Bianconi1-5/+152
Introduce EN7581 clock support to clk-en7523 driver. Add hw_init callback to en_clk_soc_data data structure. Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/57b6e53ed4d2b2e38abff6a3ea56841bad6be8a9.1712399981.git.lorenzo@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: en7523: Add en_clk_soc_data data structureLorenzo Bianconi1-13/+21
Introduce en_clk_soc_data data structure in order to define multiple clk_ops for each supported SoC. This is a preliminary patch to introduce EN7581 clock support. Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/562a0da8d7874a02a324687c152c87a1549924bd.1712399981.git.lorenzo@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-11clk: qcom: fix module autoloadingKrzysztof Kozlowski2-0/+2
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded based on the alias from of_device_id table. Clocks are considered core components, so usually they are built-in, however these can be built and used as modules on some generic kernel. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240410155356.224098-1-krzk@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-10clk: meson: fix module license to GPL onlyNeil Armstrong18-18/+18
Fix the checkpatch warning: WARNING: Prefer "GPL" over "GPL v2" - see commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20240408-amlogic-v6-9-upstream-fix-clk-module-license-v1-1-366ddc0f3db9@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-04-10clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCFNeil Armstrong2-20/+57
In order to setup the DSI clock, let's make the unused VCLK2 clock path configuration via CCF. The nocache option is removed from following clocks: - vclk2_sel - vclk2_input - vclk2_div - vclk2 - vclk_div1 - vclk2_div2_en - vclk2_div4_en - vclk2_div6_en - vclk2_div12_en - vclk2_div2 - vclk2_div4 - vclk2_div6 - vclk2_div12 - cts_encl_sel vclk2 and vclk2_div uses the newly introduced vclk regmap driver to handle the enable and reset bits. In order to set a rate on cts_encl via the vclk2 clock path, the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order to keep CCF from selection a parent. The parents of cts_encl_sel & vclk2_sel are expected to be defined in DT or manually set by the display driver at some point. The following clock scheme is to be used for DSI: xtal \_ gp0_pll_dco \_ gp0_pll |- vclk2_sel | \_ vclk2_input | \_ vclk2_div | \_ vclk2 | \_ vclk2_div1 | \_ cts_encl_sel | \_ cts_encl -> to VPU LCD Encoder |- mipi_dsi_pxclk_sel \_ mipi_dsi_pxclk_div \_ mipi_dsi_pxclk -> to DSI controller The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input. The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the DSI bitclock is the reference base clock to calculate the vclk2_div value when pixel clock is set on the cts_encl endpoint. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-3-99ecdfdc87fc@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-04-10clk: meson: add vclk driverNeil Armstrong4-0/+197
The VCLK and VCLK_DIV clocks have supplementary bits. The VCLK gate has a "SOFT RESET" bit to toggle after the whole VCLK sub-tree rate has been set, this is implemented in the gate enable callback. The VCLK_DIV clocks as enable and reset bits used to disable and reset the divider, associated with CLK_SET_RATE_GATE it ensures the rate is set while the divider is disabled and in reset mode. The VCLK_DIV enable bit isn't implemented as a gate since it's part of the divider logic and vendor does this exact sequence to ensure the divider is correctly set. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-04-10clk: rockchip: rk3588: Add reset line for HDMI ReceiverShreeya Patel1-0/+1
Export hdmirx_biu reset line required by the Synopsys DesignWare HDMIRX Controller. Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-04-10clk: rockchip: rk3568: Add missing USB480M_PHY muxDavid Jander1-0/+4
The USB480M clock can source from a MUX that selects the clock to come from either of the USB-phy internal 480MHz PLLs. These clocks are provided by the USB phy driver. Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20240404-clk-rockchip-rk3568-add-usb480m-phy-mux-v1-1-e8542afd58b9@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20240405-clk-rk3568-usb480m-phy-mux-v1-2-6c89de20a6ff@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-04-08clk: renesas: r8a779h0: Add timer clocksThanh Quan1-0/+9
Add the module clocks used by Timer (CMT/TMU) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/79a66e8ff84378d7f65d5f55cfb01b9b745edd12.1712068639.git.geert+renesas@glider.be
2024-04-08clk: Get runtime PM before walking tree for clk_summaryStephen Boyd1-2/+12
Similar to the previous commit, we should make sure that all devices are runtime resumed before printing the clk_summary through debugfs. Failure to do so would result in a deadlock if the thread is resuming a device to print clk state and that device is also runtime resuming in another thread, e.g the screen is turning on and the display driver is starting up. We remove the calls to clk_pm_runtime_{get,put}() in this path because they're superfluous now that we know the devices are runtime resumed. This also squashes a bug where the return value of clk_pm_runtime_get() wasn't checked, leading to an RPM count underflow on error paths. Fixes: 1bb294a7981c ("clk: Enable/Disable runtime PM for clk_summary") Cc: Taniya Das <quic_tdas@quicinc.com> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240325184204.745706-6-sboyd@kernel.org Reviewed-by: Douglas Anderson <dianders@chromium.org>
2024-04-08clk: Get runtime PM before walking tree during disable_unusedStephen Boyd1-12/+105
Doug reported [1] the following hung task: INFO: task swapper/0:1 blocked for more than 122 seconds. Not tainted 5.15.149-21875-gf795ebc40eb8 #1 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. task:swapper/0 state:D stack: 0 pid: 1 ppid: 0 flags:0x00000008 Call trace: __switch_to+0xf4/0x1f4 __schedule+0x418/0xb80 schedule+0x5c/0x10c rpm_resume+0xe0/0x52c rpm_resume+0x178/0x52c __pm_runtime_resume+0x58/0x98 clk_pm_runtime_get+0x30/0xb0 clk_disable_unused_subtree+0x58/0x208 clk_disable_unused_subtree+0x38/0x208 clk_disable_unused_subtree+0x38/0x208 clk_disable_unused_subtree+0x38/0x208 clk_disable_unused_subtree+0x38/0x208 clk_disable_unused+0x4c/0xe4 do_one_initcall+0xcc/0x2d8 do_initcall_level+0xa4/0x148 do_initcalls+0x5c/0x9c do_basic_setup+0x24/0x30 kernel_init_freeable+0xec/0x164 kernel_init+0x28/0x120 ret_from_fork+0x10/0x20 INFO: task kworker/u16:0:9 blocked for more than 122 seconds. Not tainted 5.15.149-21875-gf795ebc40eb8 #1 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. task:kworker/u16:0 state:D stack: 0 pid: 9 ppid: 2 flags:0x00000008 Workqueue: events_unbound deferred_probe_work_func Call trace: __switch_to+0xf4/0x1f4 __schedule+0x418/0xb80 schedule+0x5c/0x10c schedule_preempt_disabled+0x2c/0x48 __mutex_lock+0x238/0x488 __mutex_lock_slowpath+0x1c/0x28 mutex_lock+0x50/0x74 clk_prepare_lock+0x7c/0x9c clk_core_prepare_lock+0x20/0x44 clk_prepare+0x24/0x30 clk_bulk_prepare+0x40/0xb0 mdss_runtime_resume+0x54/0x1c8 pm_generic_runtime_resume+0x30/0x44 __genpd_runtime_resume+0x68/0x7c genpd_runtime_resume+0x108/0x1f4 __rpm_callback+0x84/0x144 rpm_callback+0x30/0x88 rpm_resume+0x1f4/0x52c rpm_resume+0x178/0x52c __pm_runtime_resume+0x58/0x98 __device_attach+0xe0/0x170 device_initial_probe+0x1c/0x28 bus_probe_device+0x3c/0x9c device_add+0x644/0x814 mipi_dsi_device_register_full+0xe4/0x170 devm_mipi_dsi_device_register_full+0x28/0x70 ti_sn_bridge_probe+0x1dc/0x2c0 auxiliary_bus_probe+0x4c/0x94 really_probe+0xcc/0x2c8 __driver_probe_device+0xa8/0x130 driver_probe_device+0x48/0x110 __device_attach_driver+0xa4/0xcc bus_for_each_drv+0x8c/0xd8 __device_attach+0xf8/0x170 device_initial_probe+0x1c/0x28 bus_probe_device+0x3c/0x9c deferred_probe_work_func+0x9c/0xd8 process_one_work+0x148/0x518 worker_thread+0x138/0x350 kthread+0x138/0x1e0 ret_from_fork+0x10/0x20 The first thread is walking the clk tree and calling clk_pm_runtime_get() to power on devices required to read the clk hardware via struct clk_ops::is_enabled(). This thread holds the clk prepare_lock, and is trying to runtime PM resume a device, when it finds that the device is in the process of resuming so the thread schedule()s away waiting for the device to finish resuming before continuing. The second thread is runtime PM resuming the same device, but the runtime resume callback is calling clk_prepare(), trying to grab the prepare_lock waiting on the first thread. This is a classic ABBA deadlock. To properly fix the deadlock, we must never runtime PM resume or suspend a device with the clk prepare_lock held. Actually doing that is near impossible today because the global prepare_lock would have to be dropped in the middle of the tree, the device runtime PM resumed/suspended, and then the prepare_lock grabbed again to ensure consistency of the clk tree topology. If anything changes with the clk tree in the meantime, we've lost and will need to start the operation all over again. Luckily, most of the time we're simply incrementing or decrementing the runtime PM count on an active device, so we don't have the chance to schedule away with the prepare_lock held. Let's fix this immediate problem that can be triggered more easily by simply booting on Qualcomm sc7180. Introduce a list of clk_core structures that have been registered, or are in the process of being registered, that require runtime PM to operate. Iterate this list and call clk_pm_runtime_get() on each of them without holding the prepare_lock during clk_disable_unused(). This way we can be certain that the runtime PM state of the devices will be active and resumed so we can't schedule away while walking the clk tree with the prepare_lock held. Similarly, call clk_pm_runtime_put() without the prepare_lock held to properly drop the runtime PM reference. We remove the calls to clk_pm_runtime_{get,put}() in this path because they're superfluous now that we know the devices are runtime resumed. Reported-by: Douglas Anderson <dianders@chromium.org> Closes: https://lore.kernel.org/all/20220922084322.RFC.2.I375b6b9e0a0a5348962f004beb3dafee6a12dfbb@changeid/ [1] Closes: https://issuetracker.google.com/328070191 Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Fixes: 9a34b45397e5 ("clk: Add support for runtime PM") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240325184204.745706-5-sboyd@kernel.org Reviewed-by: Douglas Anderson <dianders@chromium.org>
2024-04-08clk: Initialize struct clk_core kref earlierStephen Boyd1-15/+13
Initialize this kref once we allocate memory for the struct clk_core so that we can reuse the release function to free any memory associated with the structure. This mostly consolidates code, but also clarifies that the kref lifetime exists once the container structure (struct clk_core) is allocated instead of leaving it in a half-baked state for most of __clk_core_init(). Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240325184204.745706-4-sboyd@kernel.org
2024-04-08clk: Don't hold prepare_lock when calling kref_put()Stephen Boyd1-7/+5
We don't need to hold the prepare_lock when dropping a ref on a struct clk_core. The release function is only freeing memory and any code with a pointer reference has already unlinked anything pointing to the clk_core. This reduces the holding area of the prepare_lock a bit. Note that we also don't call free_clk() with the prepare_lock held. There isn't any reason to do that. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240325184204.745706-3-sboyd@kernel.org
2024-04-08clk: Remove prepare_lock hold assertion in __clk_release()Stephen Boyd1-2/+0
Removing this assertion lets us move the kref_put() call outside the prepare_lock section. We don't need to hold the prepare_lock here to free memory and destroy the clk_core structure. We've already unlinked the clk from the clk tree and by the time the release function runs nothing holds a reference to the clk_core anymore so anything with the pointer can't access the memory that's being freed anyway. Way back in commit 496eadf821c2 ("clk: Use lockdep asserts to find missing hold of prepare_lock") we didn't need to have this assertion either. Fixes: 496eadf821c2 ("clk: Use lockdep asserts to find missing hold of prepare_lock") Cc: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240325184204.745706-2-sboyd@kernel.org
2024-04-06clk: ti: dpll: fix incorrect #ifdef checksArnd Bergmann1-6/+4
Building with W=1 shows warnings about unused const variables like this one: drivers/clk/ti/dpll.c:99:29: error: unused variable 'omap3_dpll_core_ck_ops' [-Werror,-Wunused-const-variable] static const struct clk_ops omap3_dpll_core_ck_ops = {}; The problem is that the #ifdef checks for some of the structures in this file have gone out of sync with the code referencing them. Update these to match the current usage. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20240403080702.3509288-12-arnd@kernel.org Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-05clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210Yangyu Chen1-2/+2
Since SOC_FOO should be deprecated from patch [1], and cleanup for other SoCs is already in the mailing list [2,3,4], we remove the use of SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers, Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select when it has the symbol SOC_CANAAN_K210. [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/ [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/ Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-04-04clk: nxp: Remove an unused field in struct lpc18xx_pllChristophe JAILLET1-1/+0
In "struct lpc18xx_pll", the 'lock' field is unused. Remove it. Found with cppcheck, unusedStructMember. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/6cfb0e5251c3a59a156e70bcf6a0cc74aa764faa.1711985490.git.christophe.jaillet@wanadoo.fr Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-04-03clk: qcom: smd-rpm: Restore msm8976 num_clkAdam Skladowski1-0/+1
During rework somehow msm8976 num_clk got removed, restore it. Fixes: d6edc31f3a68 ("clk: qcom: smd-rpm: Separate out interconnect bus clocks") Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240401171641.8979-1-a39.skl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-03clk: qcom: gdsc: treat optional supplies as optionalJohan Hovold1-3/+8
Since commit deebc79b28d6 ("clk: qcom: gpucc-sc8280xp: Add external supply for GX gdsc") the GDSC supply must be treated as optional to avoid warnings like: gpu_cc-sc8280xp 3d90000.clock-controller: supply vdd-gfx not found, using dummy regulator on SC8280XP. Fortunately, the driver is already prepared to handle this by checking that the regulator pointer is non-NULL before use. This also avoids triggering a potential deadlock on SC8280XP even if the underlying issue still remains for the derivative platforms like SA8295P that actually use the supply. Fixes: deebc79b28d6 ("clk: qcom: gpucc-sc8280xp: Add external supply for GX gdsc") Link: https://lore.kernel.org/lkml/Zf25Sv2x9WaCFuIH@hovoldconsulting.com/ Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20240325085835.26158-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-02clk: renesas: r8a779h0: Add SCIF clocksGeert Uytterhoeven1-0/+4
Add the module clocks used by the Serial Communication Interfaces with FIFO (SCIF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/82d731edd4ae4a8cd7683368131095777f4fa172.1709741224.git.geert+renesas@glider.be
2024-03-31clk: samsung: exynosautov9: fix wrong pll clock id valueJaewon Kim1-4/+4
All PLL id values of CMU_TOP were incorrectly set to FOUT_SHARED0_PLL. It modified to the correct PLL clock id value. Fixes: 6587c62f69dc ("clk: samsung: add top clock support for Exynos Auto v9 SoC") Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240328091000.17660-1-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-29clk: meson: pll: print out pll name when unable to lock itDmitry Rokosov1-2/+2
In most meson systems, multiple PLLs are present, making it difficult to identify the specific PLL that fails to lock. To address this issue, print out the name of the PLL that cannot be locked. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Link: https://lore.kernel.org/r/20240328195733.30572-1-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-03-29clk: meson: s4: pll: determine maximum register in regmap configDmitry Rokosov1-0/+1
When the max_register value is not set, the regmap debugfs 'registers' file does not display the entire range of the regmap. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Link: https://lore.kernel.org/r/20240320155512.3544-5-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-03-29clk: meson: s4: peripherals: determine maximum register in regmap configDmitry Rokosov1-0/+1
When the max_register value is not set, the regmap debugfs 'registers' file does not display the entire range of the regmap. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Link: https://lore.kernel.org/r/20240320155512.3544-4-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-03-29clk: meson: a1: pll: determine maximum register in regmap configDmitry Rokosov1-0/+1
When the max_register value is not set, the regmap debugfs 'registers' file does not display the entire range of the regmap. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Link: https://lore.kernel.org/r/20240320155512.3544-3-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-03-29clk: meson: a1: peripherals: determine maximum register in regmap configDmitry Rokosov1-0/+1
When the max_register value is not set, the regmap debugfs 'registers' file does not display the entire range of the regmap. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Link: https://lore.kernel.org/r/20240320155512.3544-2-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-03-26clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1Sam Protsenko1-1/+439
Implement support for CPU clock management units: - CMU_CPUCL0: clocks for cluster 0: 4 x Cortex-A55 (cpu0..cpu3) - CMU_CPUCL1: clocks for cluster 1: 4 x Cortex-A55 (cpu4..cpu7) CPU PLLs are generating main CPU clocks for each cluster, and there are alternate ("switch") clocks that can be used temporarily while re-configuring the PLL for a new rate. ACLK, ATCLK, PCLKDBG and PERIPHCLK clocks are driving corresponding buses. CLK_CLUSTERx_SCLK are actual leaf CPU clocks and should be used to change CPU rates. Also some CoreSight clocks can be derived from DBG_USER (debug clock). PLL table was extracted from ECT table. ECT stands for "Exynos Characteristic Table", it's a Samsung specific binary data populated by BL2 bootloader in RAM at 0x90000000 address, containing PLL tables for various CMUs and other hardware specific information. The particular PLL type used in CMU_CPUCL0 and CMU_CPUCL1 (pll0822x) is an integer PLL with middle FVCO. The equation to calculate its output rate is: fout = fin * M / (P*2^S) where: fin = 26 MHz (OSCCLK frequency) M = 64..1023 P = 1..63 S = 0..6 The PLL table tries to keep "P" value low to reduce the locking time, which for pll0822x is "t = P * 150" (in OSCCLK cycles). Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240301015118.30072-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-26clk: samsung: Implement manual PLL control for ARM64 SoCsSam Protsenko2-15/+45
Some ARM64 Exynos chips are capable to control PLL clocks automatically. For those chips, whether the PLL is controlled automatically or manually is chosen in PLL_CON1 register with next bits: [28] ENABLE_AUTOMATIC_CLKGATING [1] MANUAL_PLL_CTRL [0] AUTO_PLL_CTRL The bl2 bootloader sets 0x10000001 value for some PLL_CON1 registers, which means any attempt to control those PLLs manually (e.g. disabling/enabling those PLLs or changing MUX parent clocks) would lead to PLL lock timeout with error message like this: Could not lock PLL ... At the moment, all Samsung clock drivers implement manual clock control. So in order to make it possible to control PLLs, corresponding PLL_CON1 registers should be set to 0x2 first. Some older ARM64 chips don't implement the automatic clock control though. It also might be desirable to configure some PLLs for manual control, while keeping the default configuration for the rest. So it'd convenient to choose this PLL mode for each CMU separately. Introduce .manual_plls field to CMU structure to choose the PLL control mode. Because it'll be initialized with "false" in all existing CMU structures by default, it won't affect any existing clock drivers, allowing for this feature to be enabled gradually when it's needed with no change for the rest of users. In case .manual_plls is set, set PLL_CON1 registers to manual control, akin to what's already done for gate clocks in exynos_arm64_init_clocks(). Of course, PLL_CON1 registers should be added to corresponding struct samsung_cmu_info::clk_regs array to make sure they get initialized. No functional change. This patch adds a feature, but doesn't enable it for any users. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240301015118.30072-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-26clk: renesas: r9a07g044: Mark resets array as constPaul Barker1-1/+1
The r9a07g044_resets array describes the reset signals in this SoC and does not change at runtime. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240320082831.9666-2-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-03-26clk: renesas: r9a07g043: Mark mod_clks and resets arrays as constPaul Barker1-2/+2
The r9a07g043_mod_clks and r9a07g043_resets arrays describe the module clocks and reset signals (respectively) in this SoC and do not change at runtime. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240320082831.9666-1-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-03-26clk: renesas: r8a779h0: Add thermal clockGeert Uytterhoeven1-0/+1
Add the module clock used by the Thermal Sensor/Chip Internal Voltage Monitor/Core Voltage Monitor (THS/CIVM/CVM) on the Renesas R-Car V4M (R8A779H0) SoC. Based on a patch in the BSP by Cong Dang. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/befac3e8342cd552f580d34be863ef84403c541f.1709722056.git.geert+renesas@glider.be
2024-03-19Merge tag 'soc-late-6.9' of ↵Linus Torvalds7-37/+70
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull more ARM SoC updates from Arnd Bergmann: "These are changes that for some reason ended up not making it into the first four branches but that should still make it into 6.9: - A rework of the omap clock support that touches both drivers and device tree files - The reset controller branch changes that had a dependency on late bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the drivers branch - The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree changes that got delayed and needed some extra time in linux-next for wider testing" * tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits) soc: fsl: dpio: fix kcalloc() argument order bus: ts-nbus: Improve error reporting bus: ts-nbus: Convert to atomic pwm API riscv: dts: starfive: jh7110: Add camera subsystem nodes ARM: bcm: stop selecing CONFIG_TICK_ONESHOT ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift clk: ti: Improve clksel clock bit parsing for reg property clk: ti: Handle possible address in the node name dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 dt-bindings: riscv: cpus: reg matches hart ID reset: Instantiate reset GPIO controller for shared reset-gpios reset: gpio: Add GPIO-based reset controller cpufreq: do not open-code of_phandle_args_equal() of: Add of_phandle_args_equal() helper reset: simple: add support for Sophgo SG2042 dt-bindings: reset: sophgo: support SG2042 riscv: dts: microchip: add specific compatible for mpfs pdma riscv: dts: microchip: add missing CAN bus clocks ARM: brcmstb: Add debug UART entry for 74165 ...
2024-03-15Merge tag 'clk-for-linus' of ↵Linus Torvalds131-1493/+8050
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Not a ton of stuff happening in the clk framework. We got some more devm helpers and we seem to be going in the direction of "just turn this stuff on already and leave me alone!" with the addition of a devm_clk_bulk_get_all_enable() API. I'm hoping that we can make that into a pmdomain that drivers attach instead, but this API should help drivers simplify in the meantime. Outside of the devm wrappers, we've got the usual clk driver updates that are dominated by the major phone SoC vendors (Samsung and Qualcomm) and the non-critical driver fixes for things like incorrect topology descriptions and wrong registers or bit fields. More details are below, but I'd say that it looks pretty ordinary. The only thing that really jumps out at me is the Renesas clk driver that's ignoring clks that are assigned to remote processors in DeviceTree. That's a new feature that they're using to avoid marking clks as CLK_IGNORE_UNUSED based on the configuration of the system. Core: - Increase dev_id len for clkdev lookups - Add a devm_clk_bulk_get_all_enable() API to get and enable all clks for a device - Add a devm variant of clk_rate_exclusive_get() New Drivers: - Display, TCSR, GPU, and Camera clock controllers for Qualcomm's X1 Elite SoC - Google GS101 PERIC0 and PERIC1 clock controllers - Exynos850 PDMA clocks - Exynos850 CPU cluster 0 and 1 (CMU_CPUCLK0/CMU_CPUCLK1) clock controllers Removed Drivers: - Remove the unused Qualcomm sc7180 modem clk driver Updates: - Fix some static checker errors in the Hisilicon clk driver - Polarfire MSSPLL hardware has 4 output clocks (the driver supported previously only one output); each of these 4 outputs feed dividers and the output of each divider feed individual hardware blocks (e.g. CAN, Crypto, eMMC); individual hardware block drivers need to control their clocks thus clock driver support was added for all MSSPLL output clocks - Typo fixes in the Qualcomm IPQ5018 GCC driver - Add "qdss_at" clk on Qualcomm IPQ6018, needed for WiFi - Properly terminate frequency tables in different Qualcomm clk drivers - Add MDSS, crypto, and SDCC resets on Qualcomm MSM8953 - Add missing UFS CLKREF clks on Qualcomm SC8180X - Avoid significant delays during boot by adding a softdep on rpmhpd to Qualcomm SDM845 gcc driver - Add QUPv3 RCGS w/ DFS and video resets to Qualcomm SM8150 GCC driver - Fix the custom GPU GX "do-nothing" method in the Qualcomm GDSC driver - Add an external regulator to GX GDSC on Qualcomm SC8280XP GPU clk driver - Switch display, GPU, video, and camera Qualcomm clk drivers to module_platform_driver() - Set a longer delay for Venus resets on many Qualcomm SoCs - Correct the GDSC wait times in the Qualcomm SDM845 display clk driver - Fix clock listing Oops on Amlogic axg - New pll-rate for Rockchip rk3568 - i2s rate improvements for Rockchip rk3399 - Rockchip rk3588 syscon clock fixes and removal of overall clock-number from the rk3588 binding header - A prerequisite for later improvements to the Rockchip rk3588 linked clocks - Minor clean-ups and error handling improvements in both composite-8m and SCU i.MX clock drivers - Fix for SAI_MCLK_SEL definition for i.MX8MP - Register the Samsung CMU MISC clock controller earlier, so the Multi Core Timer clocksource can use it on Google GS101 - Propagate Exynos850 SPI IPCLK rate change to parents, so the SPI will get proper clock rates - Refactor the generic Samsung CPU clock controllers code, preparing it for supporting Exynos850 CPU clocks - Fix some clk kerneldoc warnings - Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on Renesas R-Car V4M - Ignore all clocks which are assigned to a non-Linux system in the Renesas clk driver - Add watchdog clock on Renesas RZ/G3S - Add camera (CRU) clock and reset on Renesas RZ/G2UL - Add support for the Renesas R-Car V4M (R8A779H0) SoC - Convert some clk bindings to YAML so they can be validated" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits) clk: zynq: Prevent null pointer dereference caused by kmalloc failure clk: fractional-divider: Use bit operations consistently clk: fractional-divider: Move mask calculations out of lock clk: Fix clk_core_get NULL dereference clk: starfive: jh7110-vout: Convert to platform remove callback returning void clk: starfive: jh7110-isp: Convert to platform remove callback returning void clk: imx: imx8-acm: Convert to platform remove callback returning void clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk' clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk' clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe() clk: Add a devm variant of clk_rate_exclusive_get() ...
2024-03-14Merge tag 'platform-drivers-x86-v6.9-1' of ↵Linus Torvalds1-12/+1
git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86 Pull x86 platform driver updates from Ilpo Järvinen: - New acer-wmi HW support - Support for new revision of amd/pmf heartbeat notify - Correctly handle asus-wmi HW without LEDs - fujitsu-laptop battery charge control support - Support for new hp-wmi thermal profiles - Support ideapad-laptop refresh rate key - Put intel/pmc AI accelerator (GNA) into D3 if it has no driver to allow entry into low-power modes, and temporarily removed Lunar Lake SSRAM support due to breaking FW changes causing probe fail (further breaking FW changes are still pending) - Report pmc/punit_atom devices that prevent reacing low power levels - Surface Fan speed function support - Support for more sperial keys and complete the list of models with non-standard fan registers in thinkpad_acpi - New DMI touchscreen HW support - Continued modernization efforts of wmi - Removal of obsoleted ledtrig-audio call and the related dependency - Debug & metrics interface improvements - Miscellaneous cleanups / fixes / improvements * tag 'platform-drivers-x86-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: (87 commits) platform/x86/intel/pmc: Improve PKGC residency counters debug platform/x86: asus-wmi: Consider device is absent when the read is ~0 Documentation/x86/amd/hsmp: Updating urls platform/mellanox: mlxreg-hotplug: Remove redundant NULL-check platform/x86/amd/pmf: Update sps power thermals according to the platform-profiles platform/x86/amd/pmf: Add support to get sps default APTS index values platform/x86/amd/pmf: Add support to get APTS index numbers for static slider platform/x86/amd/pmf: Add support to notify sbios heart beat event platform/x86/amd/pmf: Add support to get sbios requests in PMF driver platform/x86/amd/pmf: Disable debugfs support for querying power thermals platform/x86/amd/pmf: Differentiate PMF ACPI versions x86/platform/atom: Check state of Punit managed devices on s2idle platform/x86: pmc_atom: Check state of PMC clocks on s2idle platform/x86: pmc_atom: Check state of PMC managed devices on s2idle platform/x86: pmc_atom: Annotate d3_sts register bit defines clk: x86: Move clk-pmc-atom register defines to include/linux/platform_data/x86/pmc_atom.h platform/x86: make fw_attr_class constant platform/x86/intel/tpmi: Change vsec offset to u64 platform/x86: intel_scu_pcidrv: Remove unused intel-mid.h platform/x86: intel_scu_wdt: Remove unused intel-mid.h ...
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