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2016-02-23clk: ti: dpll: convert DPLL support code to use clk_hw instead of clk ptrsTero Kristo5-26/+50
Convert DPLL support code to use clk_hw pointers for reference and bypass clocks. This allows us to use clk_hw_* APIs for accessing any required parameters for these clocks, avoiding some locking problems at least with DPLL enable code; this used clk_get_rate which uses mutex but isn't good under clk_enable / clk_disable. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-23Merge branch 'clk-fixes' into clk-nextStephen Boyd1-1/+2
* clk-fixes: clk: ti: omap3+: dpll: use non-locking version of clk_get_rate
2016-02-23clk: qcom: msm8960: fix ce3_core clk enable registerSrinivas Kandagatla1-1/+1
This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-23clk: ti: omap3+: dpll: use non-locking version of clk_get_rateTero Kristo1-1/+2
As the code in this file is being executed within irq context in some cases, we must avoid the clk_get_rate which uses mutex internally. Switch the code to use clk_hw_get_rate instead which is non-locking. This fixes an issue where PM runtime will hang the system if enabled with a serial console before a suspend-resume cycle. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Fixes: a53ad8ef3dcc ("clk: ti: Convert to clk_hw based provider APIs") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22Merge branch 'clk-samsung' into clk-nextMichael Turquette2-7/+15
2016-02-22clk: samsung: Don't build ARMv8 clock drivers on ARMv7Krzysztof Kozlowski2-3/+11
Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS so it is built also on ARMv7. This does not bring any kind of benefit. There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like multi_v7 for ARMv7). Instead build clock drivers only for respective SoC's architecture. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-19Merge branch 'clk-shmobile-for-v4.6' of ↵Michael Turquette2-0/+237
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
2016-02-19Merge branch 'clk-fixes' into clk-nextStephen Boyd12-14/+1
* clk-fixes: clk: gpio: Really allow an optional clock= DT property Revert "clk: qcom: Specify LE device endianness"
2016-02-19clk: gpio: Really allow an optional clock= DT propertyStephen Boyd1-1/+1
We mis-merged the original patch from Russell here and so the patch went almost all the way, except that we still failed to probe when there wasn't a clocks property in the DT node. Allow that case by making a negative value from of_clk_get_parent_count() into "no parents", like the original patch did. Fixes: 7ed88aa2efa5 ("clk: fix clk-gpio.c with optional clock= DT property") Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-18clk: shmobile: r8a7795: Add INTC-EX clockMagnus Damm1-0/+1
Add the "intc-ex" clock to the r8a7795 CPG MSSR driver. According to information from the hardware team the INTC-EX parent clock is CP. The next data sheet version will include this information. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-18clk: Make of_clk_get_from_provider() available to modulesAndrew F. Davis1-0/+1
Export symbol of_clk_get_from_provider so it can be used in loadable kernel modules Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-17clk: samsung: Enable COMPILE_TEST for Samsung clocksKrzysztof Kozlowski1-4/+4
Enable the COMPILE_TEST to get build coverage of some of Samsung clock controller drivers. Still some of them will be built only if appropriate SoC is chosen (like SOC_EXYNOS4415 or ARCH_S3C64XX). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-16Merge branch 'clk-bcm2835' into clk-nextMichael Turquette1-16/+9
2016-02-16clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()Eric Anholt1-11/+2
We were rolling this ourselves, but clk-divider can do it now. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-16clk: bcm2835: Fix setting of PLL divider clock ratesEric Anholt1-5/+7
Our dividers weren't being set successfully because CM_PASSWORD wasn't included in the register write. It looks easier to just compute the divider to write ourselves than to update clk-divider for the ability to OR in some arbitrary bits on write. Fixes about half of the video modes on my HDMI monitor (everything except 720x400). Cc: stable@vger.kernel.org Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-15Merge tag 'v4.6-rockchip-clk1' of ↵Michael Turquette7-153/+157
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Introduction of a factor type and a variant containing a gate to be able to also declare factor clocks in their correct place in the clock tree instead of having to register factor clocks in the init callback separately. And as always some more clock-ids and non-regression fixes for mistakes introduced in past kernel releases.
2016-02-13Revert "clk: qcom: Specify LE device endianness"Stephen Boyd11-13/+0
This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87. The commit that caused us to specify LE device endianness here, 29bb45f25ff3 (regmap-mmio: Use native endianness for read/write, 2015-10-29), has been reverted in mainline so now when we specify LE it actively breaks big endian kernels because the byte swapping in regmap-mmio is incorrect. Let's revert this change because it will 1) fix the big endian kernels and 2) be redundant to specify LE because that will become the default soon. Cc: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: mmcc8974: Use gdscs .parent and remove genpd callsRajendra Nayak1-13/+2
With gdsc driver capable of handling hierarchical power domains, specify oxili_gdsc as parent of oxilicx_gdsc. Remove all direct calls to genpd from the mmcc clock driver. The adding and removing of subdomains is now handled from within the gdsc driver. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add mmcc gdscs for msm8996 familyRajendra Nayak1-0/+157
Add all gdsc data which are part of mmcc on msm8996 family Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add GDSCs in msm8996 GCCRajendra Nayak1-0/+92
Add all data for the GDSCs which are part of msm8996 GCC block Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add support for votable gdscsRajendra Nayak2-7/+26
Some gdscs might be controlled via voting registers and might not really disable when the kernel intends to disable them (due to other votes keeping them enabled) Mark these gdscs with a flag for we do not check/wait on a disable status for these gdscs within the kernel disable callback. Also at boot, if these GDSCs are found to be ON, we make sure we vote for them before we inform the genpd framework about their status. If genpd gets no users, it then disables (removes the vote) them as part of genpd_poweroff_unused() Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add support for gdscs with gds hw controllerRajendra Nayak2-17/+29
Some gdsc power domains can have a gds_hw_controller block inside to help ensure all slave devices within the power domain are idle before the gdsc is actually switched off. This is mainly useful in power domains which host a MMU, in which case its necessary to make sure there are no outstanding MMU operations or pending bus transactions before the power domain is turned off. In gdscs with gds_hw_controller block, its necessary to check the gds_hw_ctrl status bits instead of the ones in gdscr, to determine the state of the powerdomain. While at it, also move away from using jiffies and use ktime APIs instead for busy looping on status bits. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add support for hierarchical power domainsRajendra Nayak3-10/+50
Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs specify the parents (if any) and the driver add genpd subdomains for them. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10clk: lpc32xx: add HCLK PLL output configurationSylvain Lemieux1-5/+1
This patch add the support to setup the HCLK PLL output using the "assigned-clock-rates" parameter in the device tree. If the option is not use, the clock setup by the kickstart and/or bootloader remain unchanged. The previous kernel version did not change the clock frequency output setup by the kickstart and/or bootloader; this version always setup the clock frequency output to 208MHz. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10Merge branch 'clk-fixes' into clk-nextStephen Boyd1-0/+3
* clk-fixes: clk: versatile: mask VCO bits before writing
2016-02-10clk: versatile: mask VCO bits before writingLinus Walleij1-0/+3
The Versatile syscon ICST driver OR:s the bits into place but forgets to mask the previous value, making the code only work if the register is zero or giving haphazard results. Mask the 19 bits used by the Versatile syscon interface register. Regression caused and now fixed by yours truly. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Fixes: 179c8fb3c2a6 ("clk: versatile-icst: convert to use regmap") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10clk: lpc32xx: do not register clock "0"Sylvain Lemieux1-2/+2
The following errors are display in the console during the power-on: [ 0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12 [ 0.000000] lpc32xx_clk_init: failed to register (null) clock: -12 There is no need to register clock "0"; the first clock used is 1; Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> [sboyd@codeaurora.org: s/prepare/register/] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09clk: fix __clk_init_parent() for single parent clocksMasahiro Yamada1-1/+1
Before commit b3d192d5121f ("clk: simplify __clk_init_parent()"), __clk_init_parent() called .get_parent() only for multi-parent clocks. That commit changed the behavior to call .get_parent() if available even for single-parent clocks and root clocks. It turned out a problem because there are some single-parent clocks that implement .get_parent() callback and return non-zero index. The SOCFPGA clock is the case; the commit broke the SOCFPGA boards. To keep the original behavior, invoke .get_parent() only when num_parents is greater than 1. Fixes: b3d192d5121f ("clk: simplify __clk_init_parent()") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09clk: qcom: common: check for failureSudip Mukherjee1-6/+11
We were not checking the return from devm_add_action() which can fail. Start using the helper and devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09clk: meson: Fix meson_clk_register_clks() signature type mismatchAndreas Färber1-1/+1
As preparation for arm64 based mesongxbb, which pulls in this code once enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch. The loop uses a local unsigned int variable, so adopt that type, matching the header. Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller") Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09clk: socfpga: fix __init annotationArnd Bergmann1-1/+1
clang found a bug with the __socfpga_pll_init definition: drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and global variables This moves the __init annotation to the right place so the function actually gets discarded. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09drivers/clk/Kconfig: Move the TI CDCE chips close togetherMike Looijmans1-8/+8
There are two TI CDCE clock chips in this file. Move them close together so they're easier to find. No functional change, just cosmetic. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> [sboyd@codeaurora.org: Alphabetize] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09drivers/clk/Kconfig: Fix typo "Sypport" instead of "Support"Mike Looijmans1-1/+1
Simple cosmetic fix. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09Merge branch 'clk-fixes' into clk-nextStephen Boyd6-97/+103
* clk-fixes: clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tegra: Remove improper flags for lock_enable clk: tegra: Fix divider on VI_I2C
2016-02-09Merge tag 'tegra-for-4.5-clk-fixes' of ↵Stephen Boyd6-97/+103
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes Pull tegra fixes from Thierry Reding: clk: tegra: Fixes for v4.5-rc3 This set contains a bunch of miscellaneous fixes that have accumulated over the past couple of weeks, primarily for the Tegra210 support added in v4.5-rc1. * tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tegra: Remove improper flags for lock_enable clk: tegra: Fix divider on VI_I2C
2016-02-08clk: shmobile: r8a7795: Add USB-DMAC clocksYoshihiro Shimoda1-0/+2
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-08clk: shmobile: r8a7795: Add SD divider supportDirk Behme2-0/+232
This patch adds SD[0..3] clock divider support for R-Car Gen3 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-07clk: Deprecate CLK_IS_ROOTStephen Boyd1-3/+3
We don't use CLK_IS_ROOT but in a few places in the common clk framework core. Let's replace those checks with a check for the number of parents a clk has instead of the flag, freeing up one flag for something else. We don't remove the flag yet so that things keep building, but we'll remove it once all drivers have removed their flag usage. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-07clk: gpio: Make into a platform driverStephen Boyd1-113/+52
clk_get() for DT based clks already returns EPROBE_DEFER when the OF clk provider is not present. So having all this code in the clk provider to return EPROBE_DEFER when the gpio isn't ready yet can be replaced with a platform driver that doesn't add the clk provider until the gpio can be requested. Get rid of the OF_CLK_DECLARE and convert this to a platform driver instead. Tested-by: Jyri Sarha <jsarha@ti.com> Cc: Sergej Sawazki <ce3a@gmx.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon@solid-run.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-04clk: rockchip: convert manually created factor clocks to the new typeHeiko Stuebner5-98/+24
Clean up the init code and move the creation of factor clocks to the appropriate positions coming from the clock architecture diagrams. This also unifies the artificial separation of the hclk_vcodec etc clocks again. We do keep the separate definition of some watchdog and usb480m pseudo clocks for now, as they're not real factor clocks from the clock-tree but placeholders for fixes to come (usb480m gets supplied by the missing driver for the new usbphy type and the watchdog-gate is sitting somewhere else together which we cannot model currently). Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04clk: rockchip: add a factor clock typeHeiko Stuebner2-0/+83
Add a clock type for fixed factor clocks. This allows us to define fixed factor clocks where they appear in the clock hierarchy instead of in the init function. The additional factor_gate type, finally allows us to model some last parts of the clock tree correctly. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04clk: rockchip: fix parent of hclk_vcodec on rk3036Heiko Stuebner1-1/+1
hclk_vcodec is a child of aclk_vcodec with the fixed factor clock hclk_vcodec_pre in between and not a child of hclk_disp_pre. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-03clk: rockchip: free memory in error cases when registering clock branchesShawn Lin1-2/+7
Add free memeory if rockchip_clk_register_branch fails. Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure...") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-02clk: unlock for handling unregistered clockInsu Yun1-2/+2
If clock is already unregistered, it returns with holding lock. It needs to be unlocked. Signed-off-by: Insu Yun <wuninsu@gmail.com> [sboyd@codeaurora.org: Use goto instead] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02clk: vt8500: don't return possibly uninitialized dataArnd Bergmann1-26/+65
The clk-vt8500.c driver would previously enter an endless loop when invalid settings got requested, this was now fixed. However, the driver will now return uninitialized data for a subset of those cases instead, as the gcc correctly warns: clk/clk-vt8500.c: In function 'wm8650_find_pll_bits': clk/clk-vt8500.c:423:12: error: 'best_div2' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor2 = best_div2; ^ clk/clk-vt8500.c:422:12: error: 'best_div1' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor1 = best_div1; ^ clk/clk-vt8500.c:421:14: error: 'best_mul' may be used uninitialized in this function [-Werror=maybe-uninitialized] *multiplier = best_mul; This reworks the error handling in the driver so we now return -EINVAL from clk_round_rate() and clk_set_rate() when we get impossible inputs. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 090341b0a95d ("clk: vt8500: fix sign of possible PLL values") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02clk: slightly optimize clk_core_set_parent()Masahiro Yamada1-1/+1
If clk_fetch_parent_index() fails, p_rate is unused. Move the assignment after the error checking. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02clk: simplify clk_fetch_parent_index() functionMasahiro Yamada1-16/+2
The clk_core_get_parent_by_index can be used as a helper function to simplify the implementation of clk_fetch_parent_index(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02clk: make sure parent is not NULL in clk_fetch_parent_index()Masahiro Yamada1-0/+3
If parent is given with NULL, clk_fetch_parent_index() could return a positive index value. Currently, parent is checked by the callers of this function, but it would be safer to do it in this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02clk: walk the orphan clock list more simplyMasahiro Yamada1-15/+6
This loop can be much simpler. If a new parent is available for orphan clocks, __clk_init_parent(orphan) can detect it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02clk: avoid circular clock topologyMasahiro Yamada1-0/+40
Currently, clk_register() never checks a circular parent looping, but clock providers could register such an insane clock topology. For example, "clk_a" could have "clk_b" as a parent, and vice versa. In this case, clk_core_reparent() creates a circular parent list and __clk_recalc_accuracies() calls itself recursively forever. The core infrastructure should be kind enough to bail out, showing an appropriate error message in such a case. This helps to easily find a bug in clock providers. (uh, I made such a silly mistake when I was implementing my clock providers first. I was upset because the kernel did not respond, without any error message.) This commit adds a new helper function, __clk_is_ancestor(). It returns true if the second argument is a possible ancestor of the first one. If a clock core is a possible ancestor of itself, it would make a loop when it were registered. That should be detected as an error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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