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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2018-06-02clk: tegra: no need to check return value of debugfs_create functionsGreg Kroah-Hartman1-31/+11
2018-06-02clk: davinci: no need to check return value of debugfs_create functionsGreg Kroah-Hartman1-6/+1
2018-06-02clk: bcm2835: no need to check return value of debugfs_create functionsGreg Kroah-Hartman1-4/+2
2018-06-02clk: no need to check return value of debugfs_create functionsGreg Kroah-Hartman1-99/+30
2018-06-02clk: imx6: add EPIT clock supportColin Didier1-0/+2
2018-06-01clk: mvebu: use correct bit for 98DX3236 NANDChris Packham1-1/+1
2018-06-01clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUBDaniel Lezcano1-5/+8
2018-06-01clk: imx7d: reset parent for mipi csi rootRui Miguel Silva1-0/+2
2018-06-01clk: imx7d: fix mipi dphy div parentRui Miguel Silva1-1/+1
2018-06-01clk: qcom: gcc-msm8996: Disable halt check on UFS clocksBjorn Andersson1-0/+2
2018-06-01clk: aspeed: Add 24MHz fixed clockLei YU1-1/+8
2018-06-01clk: imx7d: correct enet clock CCGR registersAnson Huang1-4/+6
2018-06-01clk: imx7d: correct enet phy ref clock gatesAnson Huang1-2/+1
2018-06-01clk: imx6sl: correct ocram_podf clock typeAnson Huang1-1/+1
2018-06-01clk: imx6sx: disable unnecessary clocks during clock initializationAnson Huang1-6/+1
2018-06-01clk: qcom: Add video clock controller driver for SDM845Amit Nischal3-0/+370
2018-06-01clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clkManu Gautam1-0/+4
2018-06-01clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabledRajendra Nayak2-12/+12
2018-06-01clk: qcom: Register the gdscs before the clocksRajendra Nayak1-16/+16
2018-06-01clk: qcom: gdsc: Add support for ALWAYS_ON gdscsRajendra Nayak2-0/+9
2018-06-01clk: berlin: switch to SPDX license identifierJisheng Zhang9-108/+9
2018-05-30clk: davinci: Fix link errors when not all SoCs are enabledDavid Lechner4-3/+50
2018-05-30clk: davinci: psc: allow for dev == NULLDavid Lechner5-18/+52
2018-05-30clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLAREDavid Lechner3-6/+21
2018-05-30clk: davinci: pll: allow dev == NULLDavid Lechner8-137/+235
2018-05-30clk: davinci: psc-dm365: fix few clocksSekhar Nori1-3/+16
2018-05-30clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabledSekhar Nori1-1/+1
2018-05-30clk: davinci: psc-dm355: fix ASP0/1 clkdev lookupsDavid Lechner1-2/+2
2018-05-30clk: davinci: pll-dm355: fix SYSCLKn parent namesDavid Lechner1-5/+5
2018-05-30clk: davinci: pll-dm355: drop pll2_sysclk2David Lechner1-4/+1
2018-05-23clk: rockchip: remove deprecated gate-clk code and dt-bindingHeiko Stuebner2-99/+0
2018-05-22clk: rockchip: use match_string() helperYisheng Xie1-11/+5
2018-05-21clk: meson: axg: let mpll clocks round closestJerome Brunet1-0/+4
2018-05-21clk: meson: mpll: add round closest supportJerome Brunet2-5/+22
2018-05-21clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl1-0/+7
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko7-8/+39
2018-05-18clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko1-4/+2
2018-05-18clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko1-0/+14
2018-05-18clk: meson: use SPDX license identifiers consistentlyJerome Brunet13-238/+20
2018-05-17clk: x86: Add ST oscout platform clockAkshu Agrawal2-1/+79
2018-05-17clk: sunxi-ng: r40: export a regmap to access the GMAC registerIcenowy Zheng1-0/+33
2018-05-17clk: sunxi-ng: r40: rewrite init code to a platform driverIcenowy Zheng1-11/+28
2018-05-16clk: at91: PLL recalc_rate() now using cached MUL and DIV valuesMarcin Ziemianowicz1-12/+1
2018-05-16clk: stm32: fix: stm32 clock drivers are not compiled by defaultGabriel Fernandez1-4/+2
2018-05-16clk: imx6ull: use OSC clock during AXI rate changeStefan Agner1-1/+1
2018-05-16clk: davinci: psc-da830: fix USB0 48MHz PHY clock registrationSekhar Nori1-1/+2
2018-05-16clk: imx: Add new clo01 and clo2 controlled by CCOSRMichael Trimarchi1-0/+18
2018-05-16clk: mediatek: add g3dsys support for MT2701 and MT7623Sean Wang3-0/+102
2018-05-16clk: mediatek: correct the clocks for MT2701 HDMI PHY moduleRyder Lee1-2/+6
2018-05-16clk: bulk: silently error out on EPROBE_DEFERJerome Brunet1-2/+3