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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2017-06-01clk: qoriq: Separate root input clock for core PLLs on ls1012aScott Wood1-14/+77
2017-06-01clk: at91: fix clk-generated parentingAlexandre Belloni1-2/+1
2017-06-01clk: imx7d: Fix the powerdown bit location of PLL DDRFabio Estevam3-1/+7
2017-06-01clk: mvebu: armada-38x: add support for 1866MHz variantsRalph Sennhauser1-3/+4
2017-06-01Merge branch 'clk-ap806' into clk-nextMichael Turquette1-36/+71
2017-06-01clk: mvebu: ap806: introduce a new bindingGregory CLEMENT1-12/+44
2017-06-01clk: mvebu: ap806: do not depend anymore of the *-clock-output-namesGregory CLEMENT1-22/+24
2017-06-01clk: mvebu: ap806: cosmetic improvementGregory CLEMENT1-7/+8
2017-05-31clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCMChen-Yu Tsai1-1/+3
2017-05-31clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCMChen-Yu Tsai1-1/+3
2017-05-29clk: meson-gxbb: Add EE 32K Clock for CECNeil Armstrong2-1/+58
2017-05-29clk: gxbb: remove CLK_IGNORE_UNUSED from clk81Jerome Brunet1-1/+1
2017-05-29clk: meson: meson8b: mark clk81 as criticalMartin Blumenstingl1-1/+1
2017-05-29clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driverMartin Blumenstingl2-62/+4
2017-05-29clk: meson-gxbb: un-export the CPU clockMartin Blumenstingl1-1/+1
2017-05-29clk: meson-gxbb: expose UART clocksHelmut Klein1-3/+3
2017-05-29clk: meson-gxbb: expose SPICC gateNeil Armstrong1-1/+1
2017-05-29clk: meson-gxbb: expose spdif master clockJerome Brunet1-2/+2
2017-05-29clk: meson-gxbb: expose i2s master clockJerome Brunet1-1/+1
2017-05-29clk: meson-gxbb: expose spdif clock gatesJerome Brunet1-2/+2
2017-05-26Merge tag 'meson-clk-fixes-for-4.12-rc2' of git://github.com/baylibre/clk-mes...Michael Turquette1-0/+1
2017-05-26clk: sunxi-ng: sun5i: Fix ahb_bist_clk definitionBoris Brezillon1-1/+1
2017-05-24clk: renesas: r8a7794: Add new CPG/MSSR driverGeert Uytterhoeven5-2/+266
2017-05-24clk: renesas: r8a7792: Add new CPG/MSSR driverGeert Uytterhoeven5-2/+232
2017-05-24clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driverGeert Uytterhoeven5-2/+302
2017-05-24clk: renesas: r8a7790: Add new CPG/MSSR driverGeert Uytterhoeven5-1/+298
2017-05-24clk: renesas: Rework Kconfig and Makefile logicGeert Uytterhoeven4-37/+135
2017-05-24clk: renesas: cpg-mssr: Initialize error pointer using ERR_PTR()Geert Uytterhoeven1-1/+1
2017-05-18clk: sunxi-ng: enable SUNXI_CCU_MP for PRCMArnd Bergmann1-0/+1
2017-05-17clk: rockchip: fix up the RK3228 clk cpu setting tableElaine Zhang1-12/+30
2017-05-16clk: meson: gxbb: fix build error without RESET_CONTROLLERTobias Regnery1-0/+1
2017-05-15clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0Geert Uytterhoeven1-13/+26
2017-05-15clk: renesas: Use pm_clk_no_clocks() helper i.s.o. direct accessGeert Uytterhoeven2-2/+2
2017-05-15clk: renesas: Do not build clk-div6 for R8A7792Geert Uytterhoeven1-1/+1
2017-05-15clk: renesas: r8a7796: Add INTC-EX clockTakeshi Kihara1-0/+1
2017-05-15clk: renesas: r8a7796: Add PCIe clocksHarunobu Kurokawa1-0/+2
2017-05-15clk: renesas: r8a7796: Add PWM clockRyo Kodama1-0/+1
2017-05-15clk: renesas: r8a7796: Add HS-USB clockKazuya Mizuguchi1-0/+1
2017-05-15clk: renesas: r8a7796: Add Sound DVC clocksKazuya Mizuguchi1-0/+2
2017-05-15clk: renesas: r8a7796: Add Sound SRC clockKazuya Mizuguchi1-0/+13
2017-05-15clk: renesas: r8a7796: Add Sound SSI clockKazuya Mizuguchi1-0/+11
2017-05-15clk: renesas: r8a7796: Add USB-DMAC clocksHiromitsu Yamasaki1-0/+2
2017-05-15clk: renesas: r8a7796: Add Audio-DMAC clocksHiromitsu Yamasaki1-0/+2
2017-05-15clk: renesas: r8a7796: Add EHCI/OHCI clocksKazuya Mizuguchi1-0/+2
2017-05-15clk: renesas: r8a7796: Add HDMI clockKoji Matsuoka1-0/+2
2017-05-15clk: renesas: r8a7795: Add HS-USB ch3 clockTakeshi Kihara1-0/+1
2017-05-15clk: renesas: r8a7795: Add USB-DMAC ch3 clockTakeshi Kihara1-0/+2
2017-05-15clk: renesas: r8a7795: Add EHCI/OHCI ch3 clockTakeshi Kihara1-0/+1
2017-05-15clk: renesas: r8a7745: Remove PLL configs for MD19=0Geert Uytterhoeven1-11/+2
2017-05-15clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocksGeert Uytterhoeven1-4/+0