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2019-06-11clk: meson: meson8b: add the cts_mclk_i958 clocksMartin Blumenstingl2-1/+69
Add the SPDIF master clock also referred as cts_mclk_i958. The setup for this clock is identical to GXBB, so this ports commit 3c277c247eabeb ("clk: meson: gxbb: add cts_mclk_i958") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11clk: meson: meson8b: add the cts_amclk clocksMartin Blumenstingl2-1/+69
Add the I2S master clock also referred as cts_amclk. The setup for this clock is identical to GXBB, so this ports commit 4087bd4b21702d ("clk: meson: gxbb: add cts_amclk") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-08clk: gcc-qcs404: Add PCIe resetsBjorn Andersson1-0/+7
Enabling PCIe requires several of the PCIe related resets from GCC, so add them all. Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: qcom: gdsc: WARN when failing to toggleBjorn Andersson1-1/+3
Failing to toggle a GDSC as the driver core is attaching the power-domain to a device will cause a silent probe deferral. Provide an explicit warning to the developer, in order to reduce the amount of time it takes to debug this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org> Tested-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: mmp: frac: Remove set but not used variable 'prev_rate'YueHaibing1-2/+1
Fixes gcc '-Wunused-but-set-variable' warning: drivers/clk/mmp/clk-frac.c: In function clk_factor_set_rate: drivers/clk/mmp/clk-frac.c:81:16: warning: variable prev_rate set but not used [-Wunused-but-set-variable] It's never used and can be removed. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: ti: Remove unused functionsYueHaibing3-146/+0
They are not used any more since commit 7558562a70fb ("clk: ti: Drop legacy clk-3xxx-legacy code") Reported-by: Hulk Robot <hulkci@huawei.com> Suggested-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: mediatek: mt8516: Remove unused variablePhilippe Mazenauer1-5/+0
Variable 'ddrphycfg_parents' is defined static and initialized, but not used in the file. ../drivers/clk/mediatek/clk-mt8516.c:234:27: warning: ‘ddrphycfg_parents’ defined but not used [-Wunused-const-variable=] static const char * const ddrphycfg_parents[] __initconst = { ^~~~~~~~~~~~~~~~~ Signed-off-by: Philippe Mazenauer <philippe.mazenauer@outlook.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil1-1/+8
The code was setting the bit 21 of the CPCCR register to use a divider of 2 for the "pll half" clock, and clearing the bit to use a divider of 1. This is the opposite of how this register field works: a cleared bit means that the /2 divider is used, and a set bit means that the divider is 1. Restore the correct behaviour using the newly introduced .div_table field. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil1-5/+24
The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: ingenic/jz4770: Fix incorrect dividers for main clocksPaul Cercueil1-6/+28
The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: ingenic/jz4740: Fix incorrect dividers for main clocksPaul Cercueil1-5/+24
The main clocks (cclk, hclk, pclk, mclk, lcd) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: ingenic: Add support for divider tablesPaul Cercueil2-6/+38
Some clocks provided on Ingenic SoCs have dividers, whose hardware value as written in the register cannot be expressed as an affine function to the actual divider value. For instance, for the CPU clock on the JZ4770, the dividers are coded as follows: ------------------ | Bits | Div | ------------------ | 0 0 0 | 1 | | 0 0 1 | 2 | | 0 1 0 | 3 | | 0 1 1 | 4 | | 1 0 0 | 6 | | 1 0 1 | 8 | | 1 1 0 | 12 | ------------------ To support this setup, we introduce a new field in the ingenic_cgu_div_info structure that allows to specify the divider table. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: keystone: sci-clk: extend clock IDs to 32 bitsTero Kristo1-8/+28
Currently, the clock identifiers are limited to 255. To support future SoCs, this muse be extended to 32 bits, which should provide way more than enough space. Basic support for extending the clock API is going to be implemented in the firmware driver, but there are some minor changes that need to be done on the clock driver side first. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-07clk: keystone: sci-clk: probe clocks from DT instead of firmwareTero Kristo2-0/+141
Probing all the available clocks from the PM firmware takes quite a lot of time, increasing boot time. Instead, implement functionality that parses only the used clocks from DT, and registers these to clock core. This way, the boot time is greatly improved. Additionally, provide a Kconfig option for parsing all the clocks from firmware, if someone requires this. It is mostly useful as a debugging functionality if we want to inspect the whole clock tree. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-07clk: keystone: sci-clk: split out the fw clock parsing to own functionTero Kristo1-27/+41
This makes it both easier to see what the probe does, and also makes it possible to add alternative implementations for the clock data source. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-07clk: keystone: sci-clk: cut down the clock name lengthTero Kristo1-4/+3
There is no need to store the full node name to the individual clocks, as this will just consome memory and make the clock debug entries unnecessary long. Just shorten this to "clk" for now. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-07clk: imx6sll: Switch to clk_hw based APIAbel Vesa1-208/+222
Switch the entire clk-imx6sll driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx7d: Switch to clk_hw based APIAbel Vesa1-484/+499
Switch the entire clk-imx7d driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6ul: Switch to clk_hw based APIAbel Vesa1-284/+290
Switch the entire clk-imx6ul driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6sx: Switch to clk_hw based APIAbel Vesa1-320/+334
Switch the entire clk-imx6sx driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6q: Switch to clk_hw based APIAbel Vesa1-367/+392
Switch the entire clk-imx6q driver to clk_hw based API. Add imx6q_obtain_fixed_clk_hw helper to clean up the registration of the clocks that are either found in device tree or are assigned a fixed zero rate. This switch allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6sl: Switch to clk_hw based APIAbel Vesa1-195/+209
Switch the entire clk-imx6sl driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: Switch wrappers to clk_hw based APIAbel Vesa1-26/+65
Switch all the wrappers to clk_hw based API and rename them to indicate that. Add macros for clk based legacy users. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: clk-fixup-mux: Switch to clk_hw based APIAbel Vesa2-5/+13
Switch the imx_clk_fixup_mux function to clk_hw based API, rename accordingly and add a macro for clk based legacy. a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: clk-fixup-div: Switch to clk_hw based APIAbel Vesa2-7/+15
Switch the imx_clk_fixup_divider function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: clk-gate-exclusive: Switch to clk_hw based APIAbel Vesa2-7/+15
Switch the imx_clk_gate_exclusive function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: clk-pfd: Switch to clk_hw based APIAbel Vesa2-6/+13
Switch the imx_clk_pfd function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: clk-pllv3: Switch to clk_hw based APIAbel Vesa2-6/+13
Switch the imx_clk_hw_pllv3 function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: clk-gate2: Switch to clk_hw based APIAbel Vesa2-6/+15
Switch the clk_register_gate2 function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: clk-cpu: Switch to clk_hw based APIAbel Vesa2-6/+13
Switch the clk_cpu clock registering function to clk_hw based API and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: clk-busy: Switch to clk_hw based APIAbel Vesa2-12/+29
Switch all the clk_busy clock registering functions to clk_hw based API. Keep around some clk based wrappers to be used by older imx platforms. This allows us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6q: Do not reparent uninitialized IMX6QDL_CLK_PERIPH2 clockAbel Vesa1-8/+0
The clock is registered later than these two re-parentings. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6sx: Do not reparent to unregistered IMX6SX_CLK_AXIAbel Vesa1-2/+0
The clock IMX6SX_CLK_AXI is not registered at all. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: Add imx_obtain_fixed_clock clk_hw based variantAbel Vesa2-0/+14
In order to move to clk_hw based API, imx_obtain_fixed_clock_hw is added. The end goal here is to have all the clk providers use the clk_hw based API. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: imx8mm: correct audio_pll2_clk to audio_pll2_outPeng Fan1-3/+3
There is no audio_pll2_clk registered, it should be audio_pll2_out. Cc: <stable@vger.kernel.org> Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: mediatek: Remove MT8183 unused clockErin Lo1-19/+0
Remove MT8183 sspm clock Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: mediatek: add audsys clock driver for MT8516Fabien Parent3-0/+72
Add audsys clock driver for MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-06clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTBFlorian Fainelli1-2/+2
ARCH_BRCMSTB needs to use the BCM2835 clock driver for chips like BCM7211 which adopted that clock controller, make that possible and the driver default to be enabled for ARCH_BRCMSTB. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-06clk: bcm: Make BCM2835 clock drivers selectableFlorian Fainelli2-2/+11
Make the BCM2835 clock driver selectable by other architectures/platforms. ARCH_BRCMSTB will be selecting that driver in the next commit since new chips like 7211 use the same CPRMAN clock controller that this driver supports. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-06clk: pwm: implement the .get_duty_cycle callbackMartin Blumenstingl1-0/+14
Commit 9fba738a53dda2 ("clk: add duty cycle support") added support for getting and setting the duty cycle of a clock. This implements the get_duty_cycle callback for PWM based clocks so the duty cycle is shown in the debugfs output (/sys/kernel/debug/clk/clk_summary). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-06clk: ti: clkctrl: Fix returning uninitialized dataTony Lindgren1-2/+5
If we do a clk_get() for a clock that does not exists, we have _ti_omap4_clkctrl_xlate() return uninitialized data if no match is found. This can be seen in some cases with SLAB_DEBUG enabled: Unable to handle kernel paging request at virtual address 5a5a5a5a ... clk_hw_create_clk.part.33 sysc_notifier_call notifier_call_chain blocking_notifier_call_chain device_add Let's fix this by setting a found flag only when we find a match. Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Fixes: 88a172526c32 ("clk: ti: add support for clkctrl clocks") Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-06clk: samsung: add new clocks for DMC for Exynos5422 SoCLukasz Luba1-6/+55
This patch provides support for clocks needed for Dynamic Memory Controller in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and GATE entries. Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-06-06clk: samsung: add BPLL rate table for Exynos 5422 SoCLukasz Luba1-1/+16
Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-06-06clk: rockchip: Remove 48 MHz PLL rate from rk3288Douglas Anderson1-1/+0
The 48 MHz PLL rate is not present in the downstream chromeos-3.14 tree. Looking at history, it was originally removed in <https://crrev.com/c/265810> ("CHROMIUM: clk: rockchip: expand more clocks support") with no explanation. Much of that patch was later reverted in <https://crrev.com/c/284595> ("CHROMIUM: clk: rockchip: Revert more questionable PLL rates"), but that patch left in the removal of 48 MHz. What I wrote in that patch: > Note that the original change also removed the rate (48000000, 1, > 64, 32) from the table. I have no idea why that was squashed in > there, but that rate was invalid anyway (it appears to have an out > of bounds NO). I'm not putting that rate in. Reading the TRM I see that NO is defined as - NO: 1, 2-16 (even only) ...and furthermore only 4 bits are assigned for NO-1, which means that the highest NO we could even represent is 16. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 445Thomas Gleixner3-27/+3
Based on 1 normalized pattern(s): this program is free software you can distribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 24 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190115.872212424@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441Thomas Gleixner5-23/+5
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation version 2 of the license extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 315 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190115.503150771@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422Thomas Gleixner5-20/+5
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 101 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190113.822954939@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 401Thomas Gleixner2-25/+2
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license v2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 2 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190111.856624369@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 372Thomas Gleixner1-5/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation version 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 135 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531081036.435762997@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 336Thomas Gleixner2-28/+2
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin st fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 246 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.674189849@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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