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2019-06-25Merge tag 'sunxi-ng-parent-rewrite-part-1-take-2' of ↵Stephen Boyd17-223/+437
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner sunxi-ng clk driver parent relation rewrite part 1 - take 2 from Chen-Yu Tsai: "The first part of ongoing work to convert the sunxi-ng clk driver from using global clock name strings to describe clk parenting, to having direct struct clk_hw pointers, or local names based on clock-names from the device tree binding. This is based on Stephen Boyd's recent work allowing clk drivers to specify clk parents using struct clk_hw * or parsing DT phandles in the clk node. This series can be split into a few major parts: 1) The first patch is a small fix for clk debugfs representation. 2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the situations I encountered, or assume I will encounter, such as single internal (struct clk_hw *) parent, single DT (struct clk_parent_data .fw_name), multiple internal parents, and multiple mixed (internal + DT) parents. A special variant for just an internal single parent is added, CLK_HW_INIT_HWS, which lets the driver share the singular list, instead of having the compiler create a compound literal every time. It might even make sense to only keep this variant. 3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale is the same as the single parent CLK_HW_INIT_* helpers. 4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references, either struct clk_hw * or DT .fw_name types, whichever the hardware requires. 5) The beginning of SUNXI_CCU_GATE conversion to local parent references. This part is not done. They are included as justification and examples for the shared list of clk parents case." * tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (25 commits) clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE clk: sunxi-ng: gate: Add macros for referencing local clock parents clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_* clk: sunxi-ng: switch to of_clk_hw_register() for registering clks clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent clk: fixed-factor: Add CLK_FIXED_FACTOR_HWS which takes list of struct clk_hw * ...
2019-06-24clk: imx8mq: Keep uart clocks on during system bootAnson Huang1-0/+10
Call imx_register_uart_clocks() API to keep uart clocks enabled when earlyprintk or earlycon is active. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-24clk: imx: Remove __init for imx_register_uart_clocks() APIAnson Huang1-3/+3
Some of i.MX SoCs' clock driver use platform driver model, and they need to call imx_register_uart_clocks() API, so imx_register_uart_clocks() API should NOT be in .init section. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-22clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATEChen-Yu Tsai1-14/+23
With the new clk parenting code and SUNXI_CCU_GATE macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_HWS as the parent clock is internal to this clock unit. To avoid duplication of clock definitions, we fix up the parent reference for A83T in the A83T init function. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATEChen-Yu Tsai1-12/+20
With the new clk parenting code and SUNXI_CCU_GATE macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_DATA to specify the parent clock. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22clk: sunxi-ng: gate: Add macros for referencing local clock parentsChen-Yu Tsai1-0/+53
With the new clk parenting code, clk_init_data was expanded to include .parent_hws, for clk drivers to directly reference parents by clk_hw, and .parent_data, for clk drivers to specify parents using a combination of device tree clock-names, pointers to struct clk_hw, device tree clocks, and/or fallback global clock names. Add four new macros: - SUNXI_CCU_GATE_HW, that can take a struct clk_hw pointer, instead of a string, as its parent. - SUNXI_CCU_GATE_FW that takes a string to match a clock-names entry in the device tree to specify the clock parent. - SUNXI_CCU_GATE_HWS that takes an array of struct clk_hw * as its parent. This allows the array to be shared with other clk declarations. - SUNXI_CCU_GATE_DATA that takes an array of struct clk_parent_data * as its parent. This allows the array to be shared with other clk declarations. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-1/+1
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-25/+44
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. A forward declaration for struct clk_fixed_factor pll_periph0_4x_clk is added as the definitions of the fixed factor clocks appear much later in the file. The position of fixed factor clock definitions will be moved for all drivers at a later time, before the conversion of all other clock types. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-15/+26
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-10/+19
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-20clk: renesas: cpg-mssr: Use [] to denote a flexible array memberGeert Uytterhoeven1-1/+1
Flexible array members should be denoted using [] instead of [0], else gcc will not warn when they are no longer at the end of the structure. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20clk: renesas: cpg-mssr: Combine driver-private and clock array allocationGeert Uytterhoeven1-14/+6
Make cpg_mssr_priv.clks[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the driver-private structure and array of available clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20clk: renesas: mstp: Combine group-private and clock array allocationGeert Uytterhoeven1-6/+6
Make mstp_clock_group.clks[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the group-private structure and array of module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20clk: renesas: div6: Combine clock-private and parent array allocationGeert Uytterhoeven1-14/+5
Make div6_clock.parents[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the clock-private structure and array of parent clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_privGeert Uytterhoeven1-1/+2
New fields were added, but kerneldoc was forgotten, or inserted at the wrong place. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner64-264/+64
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 460Thomas Gleixner1-7/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 3 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081201.897982733@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 459Thomas Gleixner1-12/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation the gpl this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license version 2 gplv2 for more details you should have received a copy of the gnu general public license version 2 gplv2 along with this source code extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 16 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081201.771169395@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19clk: samsung: Add bus clock for GPU/G3D on Exynos4412Krzysztof Kozlowski1-0/+1
Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-06-18clk: imx6q: fix section mismatch warningArnd Bergmann1-2/+3
The imx6q_obtain_fixed_clk_hw lacks an __init marker, which leads to this otherwise harmless warning: WARNING: vmlinux.o(.text+0x495358): Section mismatch in reference from the function imx6q_obtain_fixed_clk_hw() to the function .init.text:imx_obtain_fixed_clock_hw() The function imx6q_obtain_fixed_clk_hw() references the function __init imx_obtain_fixed_clock_hw(). This is often because imx6q_obtain_fixed_clk_hw lacks a __init annotation or the annotation of imx_obtain_fixed_clock_hw is wrong. Fixes: 992b703b5b38 ("clk: imx6q: Switch to clk_hw based API") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-1/+1
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-10/+19
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-17/+29
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-10/+19
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-12/+22
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-12/+22
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-14/+25
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-12/+22
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-14/+25
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*Chen-Yu Tsai1-40/+25
With the new clk parenting code and CLK_HW_INIT_* macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_HW_INIT_* definitions to describe parents using either struct clk_hw pointers or clock-names from the device tree binding. For the AR100, this also allows us to merge the generic AR100 and the A83T specific one, which only differed in the global clock names for their parent clocks. The device tree bindings used the same name specifiers. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: sunxi-ng: switch to of_clk_hw_register() for registering clksChen-Yu Tsai1-1/+1
Commit 89a5ddcc799d ("clk: Add of_clk_hw_register() API for early clk drivers") introduces a new API for registering clks, which allows the user to directly specify a device node, even if there is no struct device attached to it. The device node is used for local DT clock-names matching. Switch to of_clk_hw_register() so that local DT clock-names matching works. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: Fix debugfs clk_possible_parents for clks without parent string namesChen-Yu Tsai1-3/+41
Following the commit fc0c209c147f ("clk: Allow parents to be specified without string names"), the parent name string is not always populated. Instead, fetch the parents clk_core struct using the appropriate helper, and read its name directly. If that fails, go through the possible sources of parent names. The order in which they are used is different from how parents are looked up, with the global name having precedence over local fw_name and indices. This makes more sense as a) the parent_maps structure does not differentiate between legacy global names and fallback global names, and b) global names likely provide more information than local fw_names. Fixes: fc0c209c147f ("clk: Allow parents to be specified without string names") Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18clk: renesas: r8a774a1: Add TMU clockFabrizio Castro1-0/+5
This patch adds the TMU clocks to the R8A774A1 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18clk: renesas: r8a77995: Add CMM clocksJacopo Mondi1-0/+2
Add clock definitions for CMM units on Renesas R-Car D3. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18clk: renesas: r8a77990: Add CMM clocksJacopo Mondi1-0/+2
Add clock definitions for CMM units on Renesas R-Car E3. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18clk: renesas: r8a77965: Add CMM clocksJacopo Mondi1-0/+3
Add clock definitions for CMM units on Renesas R-Car M3-N. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18clk: renesas: r8a7795: Add CMM clocksJacopo Mondi1-0/+4
Add clock definitions for CMM units on Renesas R-Car H3. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()Anson Huang1-3/+3
i.MX8MQ clock driver uses platform driver model, better to use devm_platform_ioremap_resource() instead of of_iomap() to get IO base. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18clk: imx8mq: Use imx_check_clocks() API directlyAnson Huang1-5/+1
Use imx_check_clocks() API to check clocks directly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18clk: imx: Remove __init for imx_check_clocks() APIAnson Huang1-1/+1
Some of i.MX SoCs' clock driver use platform driver model, and they need to call imx_check_clocks() API, so imx_check_clocks() API should NOT be in .init section. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-17clk: Do a DT parent lookup even when index < 0Stephen Boyd1-1/+1
We want to allow the parent lookup to happen even if the index is some value less than 0. This may be the case if a clk provider only specifies the .name member to match a string in the "clock-names" DT property. We shouldn't require that the index be >= 0 to make this use case work. Fixes: 601b6e93304a ("clk: Allow parents to be specified via clkspec index") Reported-by: Alexandre Mergnat <amergnat@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-15clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macroHeiko Stuebner4-36/+12
Convert the boilerplate code for manual addition of the watchdog clock to the new SGRF_GATE macro for all affected socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-14clk: tegra210: Fix default rates for HDA clocksJon Hunter1-0/+2
Currently the default clock rates for the HDA and HDA2CODEC_2X clocks are both 19.2MHz. However, the default rates for these clocks should actually be 51MHz and 48MHz, respectively. The current clock settings results in a distorted output during audio playback. Correct the default clock rates for these clocks by specifying them in the clock init table for Tegra210. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-14clk: rockchip: add a type from SGRF-controlled gate clocksHeiko Stuebner1-0/+4
Some clk gates on Rockchip SoCs are part of the SGRF (secure general register files) and thus only controllable from secure mode, with the most prominent example being the watchdog. In most cases we still want to define this as a real clock though, to have complete clock tree and not reference the generic base-clock from the devicetree. So far we've just defined this as factor-1-1 clocks in the clock init, so define a special clock-type for it so that this definition can be part of the general tree-definition and save some boilerplate code. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-13Merge tag 'clk-meson-5.2-1-fixes' of https://github.com/BayLibre/clk-meson ↵Stephen Boyd3-8/+8
into clk-fixes Pull Meson clk driver fixes from Jerome Brunet: - MPLL50M DT bindings typo fix - Meson9 VPU typo fixes * tag 'clk-meson-5.2-1-fixes' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
2019-06-12clk: xgene: Don't build COMMON_CLK_XGENE by defaultMarc Gonzalez1-1/+1
Building COMMON_CLK_XGENE is pointless, unless we're building for an XGENE system. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-11clk: meson: g12a: mark fclk_div3 as criticalNeil Armstrong1-0/+10
On Amlogic Meson G12b platform, the fclk_div3 seems to be necessary for the system to operate correctly. Disabling it cause the entire system to freeze, including peripherals. Let's mark this clock as critical, fixing boot on G12b platforms. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11clk: meson: g12a: Add support for G12B CPUB clocksNeil Armstrong2-1/+801
Update the Meson G12A Clock driver to support the Amlogic G12B SoC. G12B clock driver is very close, the main differences are : - the clock tree is duplicated for the both clusters, and the SYS_PLL are swapped between the clusters - G12B has additional clocks like for CSI an other components Here only the cpu clock tree is handled. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11clk: meson-g12a: add temperature sensor clocksGuillaume La Roque2-1/+33
Add the TS clocks used by two temperature sensors Reviewed-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [fixed commit description]
2019-06-11clk: meson: meson8b: add the cts_i958 clockMartin Blumenstingl2-1/+25
Add the cts_i958 clock to control the clock source of the spdif output block. It is used to select whether the clock source of the spdif output is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer). The setup for this clock is identical to GXBB, so this ports commit 7eaa44f6207fb6 ("clk: meson: gxbb: add cts_i958 clock") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-18 19:30:01 +0300