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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2021-12-14clk: imx: use module_platform_driverMiles Chen2-2/+2
2021-12-14clk: qcom: regmap-mux: fix parent clock lookupDmitry Baryshkov3-1/+15
2021-11-26clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clkDmitry Baryshkov1-15/+0
2021-11-26clk/ast2600: Fix soc revision for AHBJoel Stanley1-5/+7
2021-11-26clk: ingenic: Fix bugs with divided dividersPaul Cercueil1-3/+3
2021-11-26clk: imx: imx6ul: Move csi_sel mux to correct base registerStefan Riedmueller1-1/+1
2021-11-18clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULLClaudiu Beznea1-2/+2
2021-11-18clk: at91: check pmc node status before registering syscore opsClément Léger1-0/+5
2021-11-18clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling pathsChristophe JAILLET1-3/+11
2021-10-20clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen1-9/+0
2021-09-30treewide: Change list_sort to use const pointersSami Tolvanen1-2/+2
2021-09-18clk: at91: clk-generated: Limit the requested rate to our rangeCodrin Ciubotariu1-0/+6
2021-09-18clk: imx8m: fix clock tree update of TF-A managed clocksAhmad Fatoum5-12/+28
2021-09-18clk: rockchip: drop GRF dependency for rk3328/rk3036 pll typesPeter Geis1-1/+1
2021-09-18clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen1-1/+1
2021-09-18clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen1-0/+9
2021-09-18clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen1-4/+4
2021-09-15clk: kirkwood: Fix a clocking boot regressionLinus Walleij1-0/+1
2021-09-03clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereferenceAdam Ford1-1/+1
2021-08-26clk: qcom: gdsc: Ensure regulator init state matches GDSC stateBjorn Andersson1-18/+36
2021-08-26clk: imx6q: fix uart earlycon unworkDong Aisheng1-1/+1
2021-08-12clk: fix leak on devm_clk_bulk_get_all() unwindBrian Norris1-1/+8
2021-08-12clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_opsDmitry Osipenko1-0/+10
2021-08-12clk: stm32f4: fix post divisor setup for I2S/SAI PLLsDario Binacchi1-5/+5
2021-07-19clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko1-5/+4
2021-07-19clk: tegra: Fix refcounting of gate clocksDmitry Osipenko2-25/+58
2021-07-19clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto1-0/+1
2021-07-19clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()Dinghao Liu1-9/+15
2021-07-14clk: si5341: Update initialization magicRobert Hancock1-1/+3
2021-07-14clk: si5341: Check for input clock presence and PLL lock on startupRobert Hancock1-0/+26
2021-07-14clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock1-2/+13
2021-07-14clk: si5341: Wait for DEVICE_READY on startupRobert Hancock1-0/+32
2021-07-14clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek1-1/+1
2021-07-14clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea1-8/+11
2021-07-14clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea1-15/+29
2021-07-14clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea1-4/+2
2021-07-14clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea1-6/+6
2021-07-14clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach1-38/+18
2021-07-14clk: vc5: fix output disabling when enabling a FODLuca Ceresoli1-3/+24
2021-07-14clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko1-1/+1
2021-07-14clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet1-1/+1
2021-07-14clk: agilex/stratix10: fix bypass representationDinh Nguyen2-21/+91
2021-07-14clk: agilex/stratix10: remove noc_clkDinh Nguyen2-34/+30
2021-07-14clk: agilex/stratix10/n5x: fix how the bypass_reg is handledDinh Nguyen1-3/+8
2021-05-19clk: exynos7: Mark aclk_fsys1_200 as criticalPaweł Chmiel1-1/+6
2021-05-14clk: uniphier: Fix potential infinite loopColin Ian King1-2/+2
2021-05-14clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLEChen Hui1-0/+1
2021-05-14clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLEChen Hui1-0/+1
2021-05-14clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enableQuanyang Wang1-1/+11
2021-05-14clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callbackQuanyang Wang1-6/+6