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path: root/drivers/clk
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2018-12-15clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter7-13/+37
The maximum frequency supported for I2S on Tegra124 and Tegra210 is 24.576MHz (as stated in the Tegra TK1 data sheet for Tegra124 and the Jetson TX1 module data sheet for Tegra210). However, the maximum I2S frequency is limited to 24MHz because that is the maximum frequency of the audio sync clock. Increase the maximum audio sync clock frequency to 24.576MHz for Tegra124 and Tegra210 in order to support 24.576MHz for I2S. Update the tegra_clk_register_sync_source() function so that it does not set the initial rate for the sync clocks and use the clock init tables to set the initial rate instead. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-15clk: tegra: get rid of duplicate definesMarcel Ziswiler1-3/+0
Get rid of 3 duplicate defines. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-15Merge branch 'clk-qcom-sdm845-lpass' into clk-nextStephen Boyd4-0/+223
- Qualcomm SDM845 audio subsystem clks * clk-qcom-sdm845-lpass: clk: qcom: Add lpass clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM LPASS clock bindings dt-bindings: clock: Update GCC bindings for protected-clocks
2018-12-15Merge branches 'clk-qcom-kconfig', 'clk-qcom-gpucc', 'clk-qcom-qcs404-rpm', ↵Stephen Boyd6-37/+324
'clk-qcom-spi' and 'clk-qcom-videocc-binding' into clk-next - Qualcomm SDM845 GPU clock controllers - Qualcomm QCS404 RPM clk support * clk-qcom-kconfig: clk: qcom: Move to menuconfig and reduce lines * clk-qcom-gpucc: dt-bindings: clock: qcom: Fix the xo parent in gpucc example clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6 clk: qcom: Add a dummy enable function for GX gdsc clk: qcom: gdsc: Don't override existing gdsc pd functions clk: qcom: Add graphics clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Graphics clock bindings * clk-qcom-qcs404-rpm: clk: qcom: smd: Add support for QCS404 rpm clocks * clk-qcom-spi: clk: qcom: msm8916: Additional clock rates for spi * clk-qcom-videocc-binding: dt-bindings: clock: Require #reset-cells in sdm845-videocc
2018-12-15Merge branches 'clk-qoriq-t1023', 'clk-protected-binding', ↵Stephen Boyd5-25/+34
'clk-define-show-macro' and 'clk-static' into clk-next - NXP QorIQ T1023 SoC support - Introduce a 'protected-clocks' binding for firmware protected clks - Shrink code some with DEFINE_SHOW_ATTRIBUTE() * clk-qoriq-t1023: clk: qoriq: add more chips support * clk-protected-binding: clk: qcom: Support 'protected-clocks' property dt-bindings: clk: Introduce 'protected-clocks' property * clk-define-show-macro: clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macro clk: nomadik: Change to use DEFINE_SHOW_ATTRIBUTE macro * clk-static: clk: stm32mp1: drop pointless static qualifier in stm32_register_hw_clk()
2018-12-15Merge branches 'clk-bcm-module-license', 'clk-boston-leak' and ↵Stephen Boyd8-10/+1087
'clk-mtk-mt7629' into clk-next - Mediatek MT7629 SoC clk controllers * clk-bcm-module-license: clk: bcm2835: make license text and module license match * clk-boston-leak: clk: boston: unregister clks on failure in clk_boston_setup() clk: boston: fix possible memory leak in clk_boston_setup() * clk-mtk-mt7629: clk: mediatek: fix the PCIe MAC clock parent clk: mediatek: Drop more __init markings for driver probe clk: mediatek: Drop __init from mtk_clk_register_cpumuxes() dt-bindings: arm: mediatek: document clk bindings for MT7629 clk: mediatek: add clock support for MT7629 SoC
2018-12-15clk: imx: add imx8qxp lpcg driverAisheng Dong3-1/+319
Add imx8qxp lpcg driver support Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-15clk: imx: add lpcg clock supportAisheng Dong3-1/+121
The Low-Power Clock Gate (LPCG) modules contain a local programming model to control the clock gates for the peripherals. An LPCG module is used to locally gate the clocks for the associated peripheral. And they're bedind the SCU clock. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-15clk: imx: add imx8qxp clk driverAisheng Dong3-0/+162
Add imx8qxp clk driver which is based on SCU firmware clock service. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Move the makefile rule higher in the file] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependantAbel Vesa3-0/+8
Remove the dependency between the i.MX8MQ CCM clock driver and the CONFIG_SOC_IMX8MQ and use CONFIG_CLK_IMX8MQ instead. CONFIG_CLK_IMX8MQ depends on ARCH_MXC && ARM64. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14clk: imx: add scu clock common partAisheng Dong4-0/+292
Add SCU clock common part which will be used by client clock drivers. SCU clocks are totally different from the legacy clocks (No much legacy things can be reused), it's using a firmware interface now based on SCU protocol. So a new configuration option CONFIG_MXC_CLK_SCU is added. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Mark ccm_ipc_handle static] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14clk: imx: add configuration option for mmio clksAisheng Dong4-2/+8
The patch introduces CONFIG_MXC_CLK option for legacy MMIO clocks, this is required to compile legacy MMIO clock conditionally when adding SCU based clocks for MX8 platforms later. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-13Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd7-71/+870
clk-meson Pull more meson clk driver updates from Neil Armstrong: - Fix GXL HDMI Pll fractional bits (from first round) - Add the Meson8/Meson8b video clocks - Add clk-input helper and use it for axg-audio clock driver * tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson: clk: meson: axg-audio: use the clk input helper function clk: meson: add clk-input helper function clk: meson: meson8b: add the read-only video clock trees clk: meson: meson8b: add the fractional divider for vid_pll_dco clk: meson: meson8b: fix the offset of vid_pll_dco's N value clk: meson: Fix GXL HDMI PLL fractional bits width
2018-12-12clk: qcom: Add missing msm8998 resetsJeffrey Hugo1-0/+2
commit c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") missed two USB2 resets. Add them. Fixes: c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: Tag basic clk types with SPDXStephen Boyd9-46/+9
These are all GPL-2.0 files per the existing license text. Replace the boiler plate with the tag. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: Tag clk core files with SPDXStephen Boyd5-32/+5
These are all GPL-2.0 files per the existing license text. Replace the boiler plate with the tag. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: meson: axg-audio: use the clk input helper functionJerome Brunet1-59/+24
Rework the axg audio clock controller to use the new clk-input helper function. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: fixed pclk input clock name to axg_audio_pclk] Link: http://lkml.kernel.org/r/20181204165819.21541-3-jbrunet@baylibre.com
2018-12-11clk: Loongson1: Remove usage of CLK_IS_BASICStephen Boyd1-3/+5
This flag doesn't look to be used by any code, just set in the clk init structure and then never tested again. Remove it from this driver as it doesn't provide any benefit. Also remove parenthesis nearby that are not needed and include clk.h to fix a sparse warning about static function definition. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: samsung: s3c2410: Remove usage of CLK_IS_BASICStephen Boyd1-1/+1
This flag doesn't look to be used by any code, just set in the clk init structure and then never tested again. Remove it from this drivers as it doesn't provide any benefit. Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: versatile: sp810: Remove usage of CLK_IS_BASICStephen Boyd1-1/+1
This flag doesn't look to be used by any code, just set in the clk init structure and then never tested again. Remove it from this driver as it doesn't provide any benefit. Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: hisilicon: Remove usage of CLK_IS_BASICStephen Boyd4-4/+4
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Jiancheng Xue <xuejiancheng@hisilicon.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Jianguo Sun <sunjianguo1@huawei.com> Cc: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: h8300: Remove usage of CLK_IS_BASICStephen Boyd1-1/+1
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: <uclinux-h8-devel@lists.sourceforge.jp> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: axm5516: Remove usage of CLK_IS_BASICStephen Boyd1-2/+0
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Anders Berg <anders.berg@lsi.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: st: Remove usage of CLK_IS_BASICStephen Boyd3-4/+4
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd5-8/+8
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: <linux-renesas-soc@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: bd718x7: Initial support for ROHM bd71837/bd71847 PMIC clockMatti Vaittinen3-0/+131
ROHM bd71837 and bd71847 contain 32768Hz clock gate. Support the clock using generic clock framework. Note, only bd71837 is tested but bd71847 should be identical what comes to clk parts. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: qcom: Move to menuconfig and reduce linesStephen Boyd1-35/+10
We duplicate the 'depends on' in almost every Kconfig here, and it's getting out of hand now that we have tens of options for various SoC drivers here. Let's clean it up a little by making a menuconfig for a submenu and adding an if wrapper around the driver section. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6q: handle ENET PLL bypassLucas Stach1-6/+57
The ENET PLL is different from the other i.MX6 PLLs, as it has multiple outputs with different post-dividers, which are all bypassed if the single bypass bit is activated. The hardware setup looks something like this: _ refclk-o---PLL---o----DIV1-----| \ | | |M |----OUT1 o-----------------------|_/ | | _ | o----DIV2-----| \ | | |M |----OUT2 o-----------------------|_/ | | _ | `----DIV3-----| \ | |M |----OUT3 `-----------------------|_/ The bypass bit not only bypasses the PLL, but also the attached post-dividers. This would be reasonbly straight forward to model with a single output, or with different bypass bits for each output, but sadly the HW guys decided that it would be good to actuate all 3 muxes with a single bit. So the need to have the PLL bypassed for one of the outputs always affects 2 other (in our model) independent branches of the clock tree. This means the decision to bypass this PLL is a system wide design choice and should not be changed on-the-fly, so we can treat any bapass configuration as static. As such we can just register the post-dividiers with a ratio that reflects the bypass status, which allows us to bypass the PLL without breaking our abstraction model and with it DT stability. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6q: optionally get CCM inputs via standard clock handlesLucas Stach1-5/+17
When specifying external clock inputs to the CCM the current code requires the clocks to be in a "clocks" child node of the DT root. This is not really conformant with DT best practices. To avoid the need to deviate from those best practices, allow the clock inputs to be specified via standard clock handles. This is in line with how drivers of the later CCM driver revisions on newer i.MX SoCs handle this. As we can't retroactively change the DT binding, allow this as an option with a fallback to the old way of how this has been handled. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6q: reset exclusive gates on initLucas Stach1-1/+5
The exclusive gates may be set up in the wrong way by software running before the clock driver comes up. In that case the exclusive setup is locked in its initial state, as the complementary function can't be activated without disabling the initial setup first. To avoid this lock situation, reset the exclusive gates to the off state and allow the kernel to provide the proper setup. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Dong Aisheng <Aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6q: add DCICx clocks gateAnson Huang1-0/+2
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks gate in CCM_CCGR0 register, add them into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6sl: ensure MMDC CH0 handshake is bypassedAnson Huang1-0/+6
Same as other i.MX6 SoCs, ensure unused MMDC channel's handshake is bypassed, this is to make sure no request signal will be generated when periphe_clk_sel is changed or SRC warm reset is triggered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: qcom: qcs404: Fix gpll0_out_main parentSrinivas Kandagatla1-1/+1
gpll0_out_main parent is cxo so fix it. Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: sunxi-ng: a64: Allow parent change for VE clockJernej Skrabec1-1/+1
Cedrus driver wants to set VE clock higher than it's possible without changing parent rate. Allow changing parent rate for VE clock, so clock rate can be set freely. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx: remove redundant initialization of ret to zeroColin Ian King1-1/+1
The initialization of ret is redundant as it is being re-assigned to the return value from the call to imx8m_clk_composite_compute_dividers. Clean this up by removing the initialization. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-07Merge tag 'clk-renesas-for-v4.21-tag2' of ↵Stephen Boyd8-33/+46
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for CPEX (timer) clocks on various R-Car Gen3 and RZ/G2 SoCs - Add support for SDHI HS400 clocks on early revisions of R-Car H3 and M3-W - Miscellaneous fixes based on the Hardware Manual Errata * tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3: Add HS400 quirk for SD clock clk: renesas: rcar-gen3: Add documentation for SD clocks clk: renesas: rcar-gen3: Set state when registering SD clocks clk: renesas: r8a77995: Simplify PLL3 multiplier/divider clk: renesas: r8a77995: Add missing CPEX clock clk: renesas: r8a77995: Remove non-existent SSP clocks clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks clk: renesas: r8a77995: Correct parent clock of DU clk: renesas: r8a77990: Correct parent clock of DU clk: renesas: r8a77970: Add CPEX clock clk: renesas: r8a77965: Add CPEX clock clk: renesas: r8a7796: Add CPEX clock clk: renesas: r8a7795: Add CPEX clock clk: renesas: r8a774a1: Add CPEX clock dt-bindings: clock: r8a7796: Remove CSIREF clock dt-bindings: clock: r8a7795: Remove CSIREF clock
2018-12-07clk: renesas: rcar-gen3: Add HS400 quirk for SD clockNiklas Söderlund1-7/+26
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400 needs a quirk to function properly. The reason for the quirk is that there are two settings which produces same divider value for the SDn clock. On the effected boards the one currently selected results in HS400 not working. This change uses the same method as the Gen2 CPG driver and simply ignores the first clock setting as this is the offending one when selecting the settings. Which of the two possible settings is used have no effect for SDR104. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-07clk: renesas: rcar-gen3: Add documentation for SD clocksNiklas Söderlund1-5/+5
Document the known use cases of the different clock settings. This is useful as different SoC and ES versions use different settings to do the same thing as there is more than one combination to achieve the same SDn clock speed. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-07clk: renesas: rcar-gen3: Set state when registering SD clocksNiklas Söderlund1-12/+4
The driver tries to figure out which state a SD clock is in when the clock is registered, instead of setting a known state. This can be problematic for two reasons. 1. If the clock driver can't figure out the state of the clock, registration of the clock fails, and setting of a known state by a clock user is not possible. 2. The state of the clock depends on if and how the bootloader configured it. The driver only checks that the rate is known, not if the clock is stopped or not for example. Fix this by setting a known state and making sure the clock is stopped. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-06clk: qcom: gcc-msm8998: Add clkref clocksBjorn Andersson1-0/+75
Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all sourced off CXO_IN, so parent them off "xo" until a proper link to the rpmcc can be described in DT. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-06clk: qcom: gcc-msm8998: Disable halt check of UFS clocksBjorn Andersson1-3/+3
Drop the halt check of the UFS symbol clocks, in accordance with other platforms. This makes clk_disable_unused() happy and makes it possible to turn the clocks on again without an error. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-06clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_atBjorn Andersson1-28/+0
Disabling gcc_hmss_dvm_bus_clk and gcc_lpass_at_clk causes the board to lock up, and by that preventing the kernel to boot without clk_ignore_unused. gcc_hmss_dvm_bus_clk is marked always-on downstream, but not referenced, and gcc_lpass_at_clk isn't mentioned. So let's remove them until they are needed by some client. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-06clk: qcom: Enumerate remaining msm8998 resetsJeffrey Hugo1-0/+87
The current list of defined resets is incomplete compared to what the hardware implements. Enumerate the remaining resets according to the hardware documentation. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-06clk: qcom: Add xo dummy clk on msm8998Stephen Boyd1-0/+15
We have this dummy factor clk in place to workaround a missing rpm clk driver that can manage the XO clk state. Add it in to match what we do on msm8996. Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Marc Gonzalez <marc.w.gonzalez@free.fr> Tested-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: mediatek: fix the PCIe MAC clock parentRyder Lee1-2/+2
The PCIe function doesn't work as the clock tree of MAC layer is wrong. Hence fix the clock table. Fixes: 3b5e748615e7 ("clk: mediatek: add clock support for MT7629 SoC") Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: apcs-msm8916: simplify probe cleanup by using devmMatti Vaittinen1-4/+2
use devm variant for of_provider registration. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> [sboyd@kernel.org: Drop unused parent pointer] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: clk-twl6040: Free of_provider at removeMatti Vaittinen1-3/+2
use devm variant for of_provider registration so provider is freed at exit. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: rk808: use managed version of of_provider registrationMatti Vaittinen1-13/+2
Simplify clean-up for rk808 by using managed version of of_provider registration. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: clk-hi655x: Free of_provider at removeMatti Vaittinen1-2/+2
use devm variant for of_provider registration so provider is freed at exit. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: of-provider: look at parent if registered device has no provider infoMatti Vaittinen1-4/+27
It seems to be usual for MFD devices that the created 'clock sub-device' do not have own DT node. The clock provider information is usually in the main device node which is owned by the MFD device. Change the devm variant of clk of-provider registration to check the parent device node if given device has no own node or if the node does not contain the #clock-cells property. In such case use the parent node if it contains the #clock-cells. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> [sboyd@kernel.org: Add some comment in the code and pull out logic into a single function to return the provider device_node pointer] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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