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path: root/drivers/clk
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2015-03-12clk: Replace of_clk_get_by_clkspec() with of_clk_get_from_provider()Stephen Boyd4-54/+18
of_clk_get_by_clkspec() has the same function signature as of_clk_get_from_provider() struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec) struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec) except of_clk_get_by_clkspec() checks to make sure clkspec is not NULL. Let's remove of_clk_get_by_clkspec() and replace the callers of it (clkconf.c) with of_clk_get_from_provider(). Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-12clk: Rename child_node to clks_node to avoid confusionStephen Boyd1-6/+6
The child_node member of struct clk is named the same as the child_node member of struct clk_core. Let's rename the struct clk's member to clks_node to avoid getting confused with the child_node member of struct clk_core and to match the name of the list head, clks. Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Alban Browaeys <alban.browaeys@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-12clk: qcom: Properly change rates for ahbix clockStephen Boyd3-3/+65
The ahbix clock can never be turned off in practice. To change the rates we need to switch the mux off the M/N counter to an always on source (XO), reprogram the M/N counter to get the rate we want and finally switch back to the M/N counter. Add a new ops structure for this type of clock so that we can set the rate properly. Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver" Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-12Merge tag 'v3.20-exynos5433-clk' of git://linuxtv.org/snawrocki/samsung into ↵Michael Turquette3-0/+5426
clk-next Clock controller driver for Exynos 5433 SoC.
2015-03-12clk: qcom: Fix i2c frequency tableStephen Boyd1-1/+1
PXO is 25MHz, not 27MHz. Fix the table. Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Andy Gross <agross@codeaurora.org> Tested-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-03-12clk: clk_set_parent() with current parent shouldn't failStephen Boyd1-4/+6
If a driver calls clk_set_parent(clk, parent) and parent is the current parent of clk we shouldn't fail in any case. Unfortunately if clk is a read-only mux we return -ENOSYS because we think we can't change the parent, except for in this special case where we don't actually need to change the parent at all. Return 0 in such a situation. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-03-12clk: Add tracepoints for hardware operationsStephen Boyd1-10/+46
It's useful to have tracepoints around operations that change the hardware state so that we can debug clock hardware performance and operations. Four basic types of events are supported: on/off events for enable, disable, prepare, unprepare that only record an event and a clock name, rate changing events for clk_set_{min_,max_}rate{_range}(), phase changing events for clk_set_phase() and parent changing events for clk_set_parent(). Cc: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-03-12clk: Missing set_phase op is an errorStephen Boyd1-8/+4
If a clock's clk_ops doesn't have the set_phase op set we should return an error from clk_set_phase(). This way clock consumers know that when they tried to set a phase it didn't work, as opposed to the current behavior where the return value is 0 meaning success. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-03-12clk: fractional-divider: support for divider bypassingHeikki Krogerus1-0/+3
If the divider or multiplier values are 0 in the register, bypassing the divider and returning the parent clock rate in clk_fd_recalc_rate(). Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed commitlog typo]
2015-03-12clk: Use lockdep asserts to find missing hold of prepare_lockKrzysztof Kozlowski1-0/+14
Add lockdep asserts for holding the prepare_lock to all functions marking this as a requirement in description. Add this to private and exported functions so all locking misuse could be detected during debugging. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-21Merge tag 'clk-for-linus-3.20' of ↵Linus Torvalds81-1191/+11680
git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
2015-02-20clk: Only recalculate the rate if neededTomeu Vizoso1-1/+4
We don't really need to recalculate the effective rate of a clock when a per-user clock is removed, if the constraints of the later aren't limiting the requested rate. This was causing problems with clocks that never had a rate set before, as rate_req would be zero. Though this could be considered a bug in the implementation of those clocks, this should be checked somewhere else. Fixes: 1c8e600440c7 ("clk: Add rate constraints to clocks") Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-18Revert "clk: mxs: Fix invalid 32-bit access to frac registers"Stefan Wahren3-31/+18
Revert commit 039e59707507 (clk: mxs: Fix invalid 32-bit access to frac registers), because it leads to a faulty spi communication on mx28evk. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-18clk: qoriq: Add support for the platform PLLEmil Medve1-0/+83
Change-Id: Iac11ed95f274485a86d2c11f32a3dc502bcd020f Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Acked-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-18clk: Replace explicit clk assignment with __clk_hw_set_clkJavier Martinez Canillas5-35/+35
The change in the clk API to return a per-user clock instance, moved the clock state to struct clk_core so now the struct clk_hw .core field is used instead of .clk for most operations. So for hardware clocks that needs to share the same clock state, both the .core and .clk pointers have to be assigned but currently only the .clk is set. This leads to NULL pointer dereference when the operations try to access the hw clock .core. For example, the composite clock rate and mux components didn't have a .core set which leads to this error: Unable to handle kernel NULL pointer dereference at virtual address 00000034 pgd = c0004000 [00000034] *pgd=00000000 Internal error: Oops: 5 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-next-20150211-00002-g1fb7f0e1150d #423 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) task: ee480000 ti: ee488000 task.ti: ee488000 PC is at clk_mux_determine_rate_flags+0x14/0x19c LR is at __clk_mux_determine_rate+0x24/0x2c pc : [<c03a355c>] lr : [<c03a3734>] psr: a0000113 sp : ee489ce8 ip : ee489d84 fp : ee489d84 r10: 0000005c r9 : 00000001 r8 : 016e3600 r7 : 00000000 r6 : 00000000 r5 : ee442200 r4 : ee440c98 r3 : ffffffff r2 : 00000000 r1 : 016e3600 r0 : ee440c98 Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c5387d Table: 4000406a DAC: 00000015 Process swapper/0 (pid: 1, stack limit = 0xee488210) Stack: (0xee489ce8 to 0xee48a000) 9ce0: 00000000 ffffffff 60000113 ee440c98 ee442200 00000000 9d00: 016e3600 ffffffff 00000001 0000005c ee489d84 c03a3734 ee489d80 ee489d84 9d20: 00000000 c048b130 00000400 c03a5798 ee489d80 ee489d84 c0607f60 ffffffea 9d40: 00000001 00000001 ee489d5c c003f844 c06e3340 ee402680 ee440d0c ed935000 9d60: 016e3600 00000003 00000001 0000005c eded3700 c03a11a0 ee489d80 ee489d84 9d80: 016e3600 ee402680 c05b413a eddc9900 016e3600 c03a1228 00000000 ffffffff 9da0: ffffffff eddc9900 016e3600 c03a1c1c ffffffff 016e3600 ed8c6710 c03d6ce4 9dc0: eded3400 00000000 00000000 c03c797c 00000001 0000005c eded3700 eded3700 9de0: 000005e0 00000001 0000005c c03db8ac c06e7e54 c03c8f08 00000000 c06e7e64 9e00: c06b6e74 c06e7f64 000005e0 c06e7df8 c06e5100 00000000 c06e7e6c c06e7f54 9e20: 00000000 00000000 eebd9550 00000000 c06e7da0 c06e7e54 ee7b5010 c06e7da0 9e40: eddc9690 c06e7db4 c06b6e74 00000097 00000000 c03d4398 00000000 ee7b5010 9e60: eebd9550 c06e7da0 00000000 c03db824 ee7b5010 fffffffe c06e7db4 c0299c7c 9e80: ee7b5010 c072a05c 00000000 c0298858 ee7b5010 c06e7db4 ee7b5044 00000000 9ea0: eddc9580 c0298a04 c06e7db4 00000000 c0298978 c02971d4 ee405c78 ee732b40 9ec0: c06e7db4 eded3800 c06d6738 c0298044 c0608300 c06e7db4 00000000 c06e7db4 9ee0: 00000000 c06beb58 c06beb58 c0299024 00000000 c068dd00 00000000 c0008944 9f00: 00000038 c049013c ee462200 c0711920 ee480000 60000113 c06c2cb0 00000000 9f20: 00000000 c06c2cb0 60000113 00000000 ef7fcafc 00000000 c0640194 c00389ec 9f40: c05ec3a8 c063f824 00000006 00000006 c06c2c50 c0696444 00000006 c0696424 9f60: c06ee1c0 c066b588 c06b6e74 00000097 00000000 c066bd44 00000006 00000006 9f80: c066b588 c003d684 00000000 c0481938 00000000 00000000 00000000 00000000 9fa0: 00000000 c0481940 00000000 c000e680 00000000 00000000 00000000 00000000 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000 [<c03a355c>] (clk_mux_determine_rate_flags) from [<c03a3734>] (__clk_mux_determine_rate+0x24/0x2c) [<c03a3734>] (__clk_mux_determine_rate) from [<c03a5798>] (clk_composite_determine_rate+0xbc/0x238) [<c03a5798>] (clk_composite_determine_rate) from [<c03a11a0>] (clk_core_round_rate_nolock+0x5c/0x9c) [<c03a11a0>] (clk_core_round_rate_nolock) from [<c03a1228>] (__clk_round_rate+0x38/0x40) [<c03a1228>] (__clk_round_rate) from [<c03a1c1c>] (clk_round_rate+0x20/0x38) [<c03a1c1c>] (clk_round_rate) from [<c03d6ce4>] (max98090_dai_set_sysclk+0x34/0x118) [<c03d6ce4>] (max98090_dai_set_sysclk) from [<c03c797c>] (snd_soc_dai_set_sysclk+0x38/0x80) [<c03c797c>] (snd_soc_dai_set_sysclk) from [<c03db8ac>] (snow_late_probe+0x24/0x48) [<c03db8ac>] (snow_late_probe) from [<c03c8f08>] (snd_soc_register_card+0xf04/0x1070) [<c03c8f08>] (snd_soc_register_card) from [<c03d4398>] (devm_snd_soc_register_card+0x30/0x64) [<c03d4398>] (devm_snd_soc_register_card) from [<c03db824>] (snow_probe+0x68/0xcc) [<c03db824>] (snow_probe) from [<c0299c7c>] (platform_drv_probe+0x48/0x98) [<c0299c7c>] (platform_drv_probe) from [<c0298858>] (driver_probe_device+0x114/0x234) [<c0298858>] (driver_probe_device) from [<c0298a04>] (__driver_attach+0x8c/0x90) [<c0298a04>] (__driver_attach) from [<c02971d4>] (bus_for_each_dev+0x54/0x88) [<c02971d4>] (bus_for_each_dev) from [<c0298044>] (bus_add_driver+0xd8/0x1cc) [<c0298044>] (bus_add_driver) from [<c0299024>] (driver_register+0x78/0xf4) [<c0299024>] (driver_register) from [<c0008944>] (do_one_initcall+0x80/0x1d0) [<c0008944>] (do_one_initcall) from [<c066bd44>] (kernel_init_freeable+0x10c/0x1d8) [<c066bd44>] (kernel_init_freeable) from [<c0481940>] (kernel_init+0x8/0xe4) [<c0481940>] (kernel_init) from [<c000e680>] (ret_from_fork+0x14/0x34) Code: e24dd00c e5907000 e1a08001 e88d000c (e5970034) The changes were made using the following cocinelle semantic patch: @i@ @@ @depends on i@ identifier dst; @@ - dst->clk = hw->clk; + __clk_hw_set_clk(dst, hw); @depends on i@ identifier dst; @@ - dst->hw.clk = hw->clk; + __clk_hw_set_clk(&dst->hw, hw); Fixes: 035a61c314eb3 ("clk: Make clk API return per-user struct clk instances") Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-18clk: Don't dereference parent clock if is NULLJavier Martinez Canillas1-2/+2
The clock passed as an argument to clk_mux_determine_rate_flags() has the CLK_SET_RATE_PARENT flag set but it has no parent, then a NULL pointer will tried to be dereferenced. This shouldn't happen since setting that flag for a clock with no parent is a bug but the core should be robust to handle that case. Fixes: 035a61c314eb3 ("clk: Make clk API return per-user struct clk instances") Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-17Merge tag 'drivers-for-linus' of ↵Linus Torvalds2-0/+219
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "These are changes for drivers that are intimately tied to some SoC and for some reason could not get merged through the respective subsystem maintainer tree. This time around, much of this is for at91, with the bulk of it being syscon and udc drivers. Also, there's: - coupled cpuidle support for Samsung Exynos4210 - Renesas 73A0 common-clk work - of/platform changes to tear down DMA mappings on device destruction - a few updates to the TI Keystone knav code" * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) cpuidle: exynos: add coupled cpuidle support for exynos4210 ARM: EXYNOS: apply S5P_CENTRAL_SEQ_OPTION fix only when necessary soc: ti: knav_qmss_queue: change knav_range_setup_acc_irq to static soc: ti: knav_qmss_queue: makefile tweak to build as dynamic module pcmcia: at91_cf: depend on !ARCH_MULTIPLATFORM soc: ti: knav_qmss_queue: export API calls for use by user driver of/platform: teardown DMA mappings on device destruction usb: gadget: at91_udc: Allocate udc instance usb: gadget: at91_udc: Update DT binding documentation usb: gadget: at91_udc: Rework for multi-platform kernel support usb: gadget: at91_udc: Simplify probe and remove functions usb: gadget: at91_udc: Remove non-DT handling code usb: gadget: at91_udc: Document DT clocks and clock-names property usb: gadget: at91_udc: Drop uclk clock usb: gadget: at91_udc: Fix clock names mfd: syscon: Add Atmel SMC binding doc mfd: syscon: Add atmel-smc registers definition mfd: syscon: Add Atmel Matrix bus DT binding documentation mfd: syscon: Add atmel-matrix registers definition clk: shmobile: fix sparse NULL pointer warning ...
2015-02-17Merge tag 'dt-for-linus' of ↵Linus Torvalds1-11/+12
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits) ARM: dts: Add PPMU node for exynos4412-trats2 ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato ARM: dts: Add PPMU dt node for exynos4 and exynos4210 ARM: dts: Add PPMU dt node for exynos3250 ARM: dts: add mipi dsi device node for exynos4415 ARM: dts: add fimd device node for exynos4415 ARM: dts: Add syscon phandle to the video-phy node for Exynos4 ARM: dts: Add sound nodes for exynos4412-trats2 ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2 ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi ARM: dts: Add max77693 charger node for exynos4412-trats2 ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2 ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2 ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2 ARM: dts: am57xx-beagle-x15: Fix USB2 mode ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ...
2015-02-17Merge tag 'soc-for-linus' of ↵Linus Torvalds2-0/+10
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "New and updated SoC support. Also included are some cleanups where the platform maintainers hadn't separated cleanups from new developent in separate branches. Some of the larger things worth pointing out: - A large set of changes from Alexandre Belloni and Nicolas Ferre preparing at91 platforms for multiplatform and cleaning up quite a bit in the process. - Removal of CSR's "Marco" SoC platform that never made it out to the market. We love seeing these since it means the vendor published support before product was out, which is exactly what we want! New platforms this release are: - Conexant Digicolor (CX92755 SoC) - Hisilicon HiP01 SoC - CSR/sirf Atlas7 SoC - ST STiH418 SoC - Common code changes for Nvidia Tegra132 (64-bit SoC) We're seeing more and more platforms having a harder time labelling changes as cleanups vs new development -- which is a good sign that we've come quite far on the cleanup effort. So over time we might start combining the cleanup and new-development branches more" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits) ARM: at91/trivial: unify functions and machine names ARM: at91: remove at91_dt_initialize and machine init_early() ARM: at91: change board files into SoC files ARM: at91: remove at91_boot_soc ARM: at91: move alternative initial mapping to board-dt-sama5.c ARM: at91: merge all SOC_AT91SAM9xxx ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init() ARM: digicolor: select syscon and timer ARM: zynq: Simplify SLCR initialization ARM: zynq: PM: Fixed simple typo. ARM: zynq: Setup default gpio number for Xilinx Zynq ARM: digicolor: add low level debug support ARM: initial support for Conexant Digicolor CX92755 SoC ARM: OMAP2+: Add dm816x hwmod support ARM: OMAP2+: Add clock domain support for dm816x ARM: OMAP2+: Add board-generic.c entry for ti81xx ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage ARM: at91: remove unused mach/system_rev.h ARM: at91: stop using HAVE_AT91_DBGUx ARM: at91: fix ordering of SRAM and PM initialization ...
2015-02-14clk: convert clock name allocations to kstrdup_constAndrzej Hajda1-6/+6
Clock subsystem frequently performs duplication of strings located in read-only memory section. Replacing kstrdup by kstrdup_const allows to avoid such operations. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: Christoph Lameter <cl@linux.com> Cc: Pekka Enberg <penberg@kernel.org> Cc: David Rientjes <rientjes@google.com> Cc: Joonsoo Kim <iamjoonsoo.kim@lge.com> Cc: Tejun Heo <tj@kernel.org> Cc: Greg KH <greg@kroah.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2015-02-11Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-nextLinus Torvalds1-7/+7
Pull networking updates from David Miller: 1) More iov_iter conversion work from Al Viro. [ The "crypto: switch af_alg_make_sg() to iov_iter" commit was wrong, and this pull actually adds an extra commit on top of the branch I'm pulling to fix that up, so that the pre-merge state is ok. - Linus ] 2) Various optimizations to the ipv4 forwarding information base trie lookup implementation. From Alexander Duyck. 3) Remove sock_iocb altogether, from CHristoph Hellwig. 4) Allow congestion control algorithm selection via routing metrics. From Daniel Borkmann. 5) Make ipv4 uncached route list per-cpu, from Eric Dumazet. 6) Handle rfs hash collisions more gracefully, also from Eric Dumazet. 7) Add xmit_more support to r8169, e1000, and e1000e drivers. From Florian Westphal. 8) Transparent Ethernet Bridging support for GRO, from Jesse Gross. 9) Add BPF packet actions to packet scheduler, from Jiri Pirko. 10) Add support for uniqu flow IDs to openvswitch, from Joe Stringer. 11) New NetCP ethernet driver, from Muralidharan Karicheri and Wingman Kwok. 12) More sanely handle out-of-window dupacks, which can result in serious ACK storms. From Neal Cardwell. 13) Various rhashtable bug fixes and enhancements, from Herbert Xu, Patrick McHardy, and Thomas Graf. 14) Support xmit_more in be2net, from Sathya Perla. 15) Group Policy extensions for vxlan, from Thomas Graf. 16) Remove Checksum Offload support for vxlan, from Tom Herbert. 17) Like ipv4, support lockless transmit over ipv6 UDP sockets. From Vlad Yasevich. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1494+1 commits) crypto: fix af_alg_make_sg() conversion to iov_iter ipv4: Namespecify TCP PMTU mechanism i40e: Fix for stats init function call in Rx setup tcp: don't include Fast Open option in SYN-ACK on pure SYN-data openvswitch: Only set TUNNEL_VXLAN_OPT if VXLAN-GBP metadata is set ipv6: Make __ipv6_select_ident static ipv6: Fix fragment id assignment on LE arches. bridge: Fix inability to add non-vlan fdb entry net: Mellanox: Delete unnecessary checks before the function call "vunmap" cxgb4: Add support in cxgb4 to get expansion rom version via ethtool ethtool: rename reserved1 memeber in ethtool_drvinfo for expansion ROM version net: dsa: Remove redundant phy_attach() IB/mlx4: Reset flow support for IB kernel ULPs IB/mlx4: Always use the correct port for mirrored multicast attachments net/bonding: Fix potential bad memory access during bonding events tipc: remove tipc_snprintf tipc: nl compat add noop and remove legacy nl framework tipc: convert legacy nl stats show to nl compat tipc: convert legacy nl net id get to nl compat tipc: convert legacy nl net id set to nl compat ...
2015-02-07clkdev: Always allocate a struct clk and call __clk_get() w/ CCFStephen Boyd3-37/+59
of_clk_get_by_clkspec() returns a struct clk pointer but it doesn't create a new handle for the consumers when we're using the common clock framework. Instead it just returns whatever the clk provider hands out. When the consumers go to call clk_put() we get an Oops. Unable to handle kernel paging request at virtual address 00200200 pgd = c0004000 [00200200] *pgd=00000000 Internal error: Oops: 805 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-rc1-00104-ga251361a-dirty #992 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) task: ee00b000 ti: ee088000 task.ti: ee088000 PC is at __clk_put+0x24/0xd0 LR is at clk_prepare_lock+0xc/0xec pc : [<c03eef38>] lr : [<c03ec1f4>] psr: 20000153 sp : ee089de8 ip : 00000000 fp : 00000000 r10: ee02f480 r9 : 00000001 r8 : 00000000 r7 : ee031cc0 r6 : ee089e08 r5 : 00000000 r4 : ee02f480 r3 : 00100100 r2 : 00200200 r1 : 0000091e r0 : 00000001 Flags: nzCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment kernel Control: 10c5387d Table: 4000404a DAC: 00000015 Process swapper/0 (pid: 1, stack limit = 0xee088238) Stack: (0xee089de8 to 0xee08a000) 9de0: ee7c8f14 c03f0ec8 ee089e08 00000000 c0718dc8 00000001 9e00: 00000000 c04ee0f0 ee7e0844 00000001 00000181 c04edb58 ee2bd320 00000000 9e20: 00000000 c011dc5c ee16a1e0 00000000 00000000 c0718dc8 ee16a1e0 ee2bd1e0 9e40: c0641740 ee16a1e0 00000000 ee2bd320 c0718dc8 ee1d3e10 ee1d3e10 00000000 9e60: c0769a88 00000000 c0718dc8 00000000 00000000 c02c3124 c02c310c ee1d3e10 9e80: c07b4eec 00000000 c0769a88 c02c1d0c ee1d3e10 c0769a88 ee1d3e44 00000000 9ea0: c07091dc c02c1eb8 00000000 c0769a88 c02c1e2c c02c0544 ee005478 ee1676c0 9ec0: c0769a88 ee3a4e80 c0760ce8 c02c150c c0669b90 c0769a88 c0746cd8 c0769a88 9ee0: c0746cd8 ee2bc4c0 c0778c00 c02c24e0 00000000 c0746cd8 c0746cd8 c07091f0 9f00: 00000000 c0008944 c04f405c 00000025 ee00b000 60000153 c074ab00 00000000 9f20: 00000000 c074ab90 60000153 00000000 ef7fca5d c050860c 000000b6 c0036b88 9f40: c065ecc4 c06bc728 00000006 00000006 c074ab30 ef7fca40 c0739bdc 00000006 9f60: c0718dbc c0778c00 000000b6 c0718dc8 c06ed598 c06edd64 00000006 00000006 9f80: c06ed598 c003b438 00000000 c04e64f4 00000000 00000000 00000000 00000000 9fa0: 00000000 c04e64fc 00000000 c000e838 00000000 00000000 00000000 00000000 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 c0c0c0c0 c0c0c0c0 [<c03eef38>] (__clk_put) from [<c03f0ec8>] (of_clk_set_defaults+0xe0/0x2c0) [<c03f0ec8>] (of_clk_set_defaults) from [<c02c3124>] (platform_drv_probe+0x18/0xa4) [<c02c3124>] (platform_drv_probe) from [<c02c1d0c>] (driver_probe_device+0x10c/0x22c) [<c02c1d0c>] (driver_probe_device) from [<c02c1eb8>] (__driver_attach+0x8c/0x90) [<c02c1eb8>] (__driver_attach) from [<c02c0544>] (bus_for_each_dev+0x54/0x88) [<c02c0544>] (bus_for_each_dev) from [<c02c150c>] (bus_add_driver+0xd4/0x1d0) [<c02c150c>] (bus_add_driver) from [<c02c24e0>] (driver_register+0x78/0xf4) [<c02c24e0>] (driver_register) from [<c07091f0>] (fimc_md_init+0x14/0x30) [<c07091f0>] (fimc_md_init) from [<c0008944>] (do_one_initcall+0x80/0x1d0) [<c0008944>] (do_one_initcall) from [<c06edd64>] (kernel_init_freeable+0x108/0x1d4) [<c06edd64>] (kernel_init_freeable) from [<c04e64fc>] (kernel_init+0x8/0xec) [<c04e64fc>] (kernel_init) from [<c000e838>] (ret_from_fork+0x14/0x3c) Code: ebfff4ae e5943014 e5942018 e3530000 (e5823000) Let's create a per-user handle here so that clk_put() can properly unlink it and free the handle. Now that we allocate a clk structure here we need to free it if __clk_get() fails so bury the __clk_get() call in __of_clk_get_from_provider(). We need to handle the same problem in clk_get_sys() so export __clk_free_clk() to clkdev.c and do the same thing, except let's use a union to make this code #ifdef free. This fixes the above crash, properly calls __clk_get() when of_clk_get_from_provider() is called, and cleans up the clk structure on the error path of clk_get_sys(). Fixes: 035a61c314eb "clk: Make clk API return per-user struct clk instances" Reported-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reported-by: Alban Browaeys <alban.browaeys@gmail.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Alban Browaeys <prahal@yahoo.com> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-05clk: samsung: exynos5433: Move CLK_SCLK_HDMI_SPDIF_DISP clock to CMU_TOP domainChanwoo Choi1-5/+5
This patch fixes the bug of CLK_SCLK_HDMI_SPDIF_DISP clock because this clock should be included in CMU_TOP domain. So, this patch moves the CLK_SCLK_HDMI_ SPDIF_DISP clock from CMU_MIF to CMU_TOP domain. Reported-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: samsung: Add CLKOUT driver support for Exynos5433 SoCInha Song1-0/+2
This patch add CLKOUT driver support for Exynos5433 SoC. Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: samsung: exynos5433: Add clocks for CMU_CAM1 domainChanwoo Choi1-0/+435
This patch adds the mux/divider/gate clocks for CMU_CAM1 domain which generates the clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: samsung: exynos5433: Add clocks for CMU_CAM0 domainChanwoo Choi1-0/+501
This patch adds the mux/divider/gate clocks for CMU_CAM0 domain which generates the clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: samsung: exynos5433: Add clocks for CMU_ISP domainChanwoo Choi1-0/+267
This patch adds the mux/divider/gate clocks for CMU_ISP domain which generates the clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: samsung: exynos5433: Add clocks for CMU_HEVC domainChanwoo Choi1-0/+115
This patch adds the mux/divider/gate clocks for CMU_HEVC domain which generates the clocks for HEVC(High Efficiency Video Codec) decoder IP. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: samsung: exynos5433: Add clocks for CMU_MFC domainChanwoo Choi1-0/+113
This patch adds the mux/divider/gate clocks for CMU_MFC domain which generates the clocks for MFC(Multi-Format Codec) IP. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: samsung: exynos5433: Add clocks for CMU_MSCL domainChanwoo Choi1-0/+185
This patch adds the mux/divider/gate clocks for CMU_MSCL domain which generates the clocks for M2M (Memory to Memory) scaler, JPEG IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: samsung: exynos5433: Add clocks for CMU_ATLAS domainChanwoo Choi1-0/+219
This patch adds the mux/divider/gate clocks for CMU_ATLAS domain which generates the clocks for Cortex-A57 Quad-core processsor, L2 cache controller and CoreSight. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: samsung: exynos5433: Add clocks for CMU_APOLLO domainChanwoo Choi1-0/+193
This patch adds the mux/divider/gate clocks for CMU_APOLLO domain which generates the clocks for Cortex-A53 Quad-core processsor. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> [s.nawrocki@samsung.com: Renamed pclk_pmu_sysreg_apollo to pclk_sysreg_apollo] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-05clk: shmobile: div6: Avoid division by zero in .round_rate()Geert Uytterhoeven1-0/+3
Anyone may call clk_round_rate() with a zero rate value, so we have to protect against that. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-04clk: samsung: exynos5433: Add clocks for CMU_GSCL domainChanwoo Choi1-0/+146
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler clocks. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add clocks for CMU_G3D domainChanwoo Choi1-0/+127
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains the clocks for GPU(3D Graphics Engine). Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domainChanwoo Choi1-0/+302
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domainsChanwoo Choi1-0/+187
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains which contain global data buses clocked at up the 400MHz. These blocks transfer data between DRAM and various sub-blocks. These clock domains also contain global peripheral buses clocked at 67/111/200/222/266/333/400 MHz and used for register accesses. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add clocks for CMU_AUD domainChanwoo Choi1-0/+172
This patch adds the mux/divider/gate clocks for CMU_AUD domain which includes the clocks of Cortex-A5/Bus/Audio clocks. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add clocks for CMU_DISP domainChanwoo Choi1-0/+437
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which includes clocks of the display IPs (DECON/HDMI/DSIM/MIXER). Also, CMU_DISP requires 'sclk_hdmi_spdif_disp' source clock from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add clocks for CMU_MIF domainChanwoo Choi1-0/+599
This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect). The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add clocks for CMU_G2D domainChanwoo Choi1-0/+146
This patch adds ths mux/divider/gate clocks of CMU_G2D domain which includes G2D/MDMA IPs. The CMU_G2D requires its parent defined in the CMU_TOP domain. Hence this patch adds G2D related clocks to the CMU_TOP domain. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add clocks for CMU_PERIS domainChanwoo Choi1-2/+149
This patch adds missing gate clocks of CMU_PERIS domain which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs. The special clocks of CMU_PERIS use oscclk source clock directly. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add clocks for CMU_PERIC domainChanwoo Choi1-2/+81
This patch adds missing divider/gate clocks of CMU_PERIC domain which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use external input clock which has 'ioclk_*' prefix. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on] Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domainChanwoo Choi1-0/+90
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433. CMU_TOP domain provides source clocks to other CMU domains. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: samsung: exynos5433: Add clocks using common clock frameworkChanwoo Choi2-0/+964
This patch adds support for the CMU (Clock Management Units) of Exynos5433 which is an Octa-core 64bit SoC. This patch supports necessary clocks (PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation for Exynos5433 clock controller. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> [s.nawrocki@samsung.com: whitespace cleanup in dt-bindings/clock/exynos5433.h] [ added U suffix to first arguments of PLL_35XX_RATE()] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04clk: mxs: Fix invalid 32-bit access to frac registersStefan Wahren3-18/+31
According to i.MX23 and i.MX28 reference manual [1],[2] the fractional clock control register is 32-bit wide, but is separated in 4 parts. So write instructions must not apply to more than 1 part at once. The clk init for the i.MX28 violates this restriction and all the other accesses on that register suggest that there isn't such a restriction. This patch restricts the access to this register to byte instructions and extends the comment in the init functions. Btw the imx23 init now uses a R-M-W sequence just like imx28 init to avoid any clock glitches. The changes has been tested with a i.MX23 and a i.MX28 board. [1] - http://cache.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf [2] - http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-03clk: omap: compile legacy omap3 clocks conditionallyArnd Bergmann6-2/+14
The 'ARM: OMAP3: legacy clock data move under clk driver' patch series causes build errors when CONFIG_OMAP3 is not set: drivers/clk/ti/dpll.c: In function 'ti_clk_register_dpll': drivers/clk/ti/dpll.c:199:31: error: 'omap3_dpll_ck_ops' undeclared (first use in this function) const struct clk_ops *ops = &omap3_dpll_ck_ops; ^ drivers/clk/ti/dpll.c:199:31: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/ti/dpll.c:259:10: error: 'omap3_dpll_per_ck_ops' undeclared (first use in this function) ops = &omap3_dpll_per_ck_ops; ^ drivers/built-in.o: In function `ti_clk_register_gate': drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_omap3430es2_dss_usbhost_wait' drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_am35xx_ipss_module_wait' -in.o: In function `ti_clk_register_interface': drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_hsotgusb_wait' drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_dss_usbhost_wait' drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_ssi_wait' drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_am35xx_ipss_wait' drivers/built-in.o: In function `ti_clk_register_composite': :(.text+0x3da768): undefined reference to `ti_clk_build_component_gate' In order to fix that problem, this patch makes the omap3 legacy code compiled only when both CONFIG_OMAP3 and CONFIG_ATAGS are set. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-03Merge tag 'tegra-clk-3.20' of ↵Michael Turquette7-52/+172
git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next Tegra clock fixes for 3.20
2015-02-03Merge tag 'v3.20-exynos-clk' of git://linuxtv.org/snawrocki/samsung into ↵Michael Turquette5-347/+112
clk-next Exynos 3250, 4415 drivers cleanup by using common code and addition of clock definitions for DVFS on Exynos4.
2015-02-03clkdev: Export clk_register_clkdevTomeu Vizoso1-0/+1
So it can be used from modules such as clk-test.ko. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-24 23:53:20 +0300