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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2021-03-04clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLsAngeloGioacchino Del Regno1-50/+50
2021-03-04clk: sunxi-ng: h6: Fix clock divider range on some clocksAndre Przywara1-4/+4
2021-03-04clk: sunxi-ng: h6: Fix CEC clockAndre Przywara1-1/+1
2021-03-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl1-1/+1
2021-01-27clk: tegra30: Add hda clock default rates to clock driverPeter Geis1-0/+2
2020-12-30clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9Terry Zhou1-2/+2
2020-12-30clk: sunxi-ng: Make sure divider tables have sentinelJernej Skrabec2-0/+2
2020-12-30clk: s2mps11: Fix a resource leak in error handling paths in the probe functionChristophe JAILLET1-0/+1
2020-12-30clk: ti: Fix memleak in ti_fapll_synth_setupZhang Qilong1-2/+9
2020-12-30clk: tegra: Fix duplicated SE clock entryDmitry Osipenko2-1/+2
2020-12-30clk: renesas: r9a06g032: Drop __packed for portabilityGeert Uytterhoeven1-1/+1
2020-11-05clk: ti: clockdomain: fix static checker warningTero Kristo1-0/+2
2020-10-30clk: bcm2835: add missing release if devm_clk_hw_register failsNavid Emamdoost1-1/+3
2020-10-30clk: at91: clk-main: update key before writing AT91_CKGR_MORClaudiu Beznea1-3/+8
2020-10-30clk: rockchip: Initialize hw to error to avoid undefined behaviorStephen Boyd1-1/+1
2020-10-07clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSEDMarek Szyprowski1-2/+2
2020-10-07clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clkDinh Nguyen1-1/+1
2020-10-01clk: stratix10: use do_div() for 64-bit calculationDinh Nguyen1-1/+3
2020-10-01clk/ti/adpll: allocate room for terminating nullStephen Kitt1-9/+2
2020-09-23clk: rockchip: Fix initialization of mux_pll_src_4plls_pNathan Chancellor1-1/+1
2020-09-23clk: davinci: Use the correct size when allocating memoryChristophe JAILLET1-1/+1
2020-08-26clk: Evict unregistered clks from parent cachesStephen Boyd1-11/+41
2020-08-21clk: clk-atlas6: fix return value check in atlas6_clk_init()Xu Wang1-1/+1
2020-08-19clk: scmi: Fix min and max rate when registering clocks with discrete ratesSudeep Holla1-3/+19
2020-06-25clk: sprd: return correct type of value for _sprd_pll_recalc_rateChunyan Zhang1-1/+1
2020-06-25clk: bcm2835: Fix return type of bcm2835_register_gateNathan Chancellor1-5/+5
2020-06-25clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1Marek Szyprowski1-1/+2
2020-06-25clk: ti: composite: fix memory leakTero Kristo1-0/+1
2020-06-25clk: clk-flexgen: fix clock-critical handlingAlain Volmat1-0/+1
2020-06-25clk: samsung: Mark top ISP and CAM clocks on Exynos542x as criticalMarek Szyprowski1-7/+9
2020-06-25clk: qcom: msm8916: Fix the address location of pll->config_regBryan O'Donoghue1-4/+4
2020-06-25clk: sunxi: Fix incorrect usage of round_down()Rikard Falkeborn1-1/+1
2020-06-22PM: runtime: clk: Fix clk_pm_runtime_get() error pathRafael J. Wysocki1-1/+5
2020-05-20clk: Unlink clock if failed to prepare or enableMarc Zyngier1-0/+3
2020-05-20clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocksJustin Swartz1-13/+4
2020-04-23clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni1-6/+6
2020-04-23clk: at91: usb: continue if clk_hw_round_rate() return zeroClaudiu Beznea1-0/+3
2020-04-17clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil1-1/+3
2020-04-13clk: qcom: rcg: Return failure for RCG updateTaniya Das1-1/+1
2020-02-24clk: uniphier: Add SCSSI clock gate for each channelKunihiko Hayashi1-5/+8
2020-02-24clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng1-1/+27
2020-02-24clk: qcom: rcg2: Don't crash if our parent can't be found; return an errorDouglas Anderson1-0/+3
2020-02-11clk: tegra: Mark fuse clock as criticalStephen Warren1-1/+5
2020-02-05clk: mmp2: Fix the order of timer mux parentsLubomir Rintel1-1/+1
2020-02-05clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent orderSamuel Holland1-2/+2
2020-01-27clk: actions: Fix factor clk struct member accessManivannan Sadhasivam1-4/+3
2020-01-27clk: sunxi-ng: v3s: add the missing PLL_DDR1Icenowy Zheng2-6/+19
2020-01-27clk: qcom: Fix -Wunused-const-variableNathan Huckleberry1-36/+0
2020-01-27clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate registerOndrej Jirman1-1/+1
2020-01-27clk: meson: axg: spread spectrum is on mpll2Jerome Brunet1-5/+5