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path: root/drivers/clk
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2014-01-18clk: ti: add support for TI fixed factor clockTero Kristo2-1/+68
2014-01-18CLK: ti: add support for ti divider-clockTero Kristo3-2/+489
2014-01-18clk: ti: add composite clock supportTero Kristo2-1/+270
2014-01-18CLK: TI: add autoidle supportTero Kristo2-1/+134
2014-01-18CLK: TI: Add DPLL clock supportTero Kristo2-0/+559
2014-01-18CLK: ti: add init support for clock IP blocksTero Kristo2-3/+113
2014-01-18CLK: TI: add DT alias clock registration mechanismTero Kristo3-0/+59
2014-01-17Merge remote-tracking branch 'linaro/clk-next' into clk-nextMike Turquette79-4556/+24939
2014-01-17clk: qcom: Add support for MSM8660's global clock controller (GCC)Stephen Boyd3-0/+2828
2014-01-17clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)Stephen Boyd3-0/+2635
2014-01-17clk: qcom: Add support for MSM8974's global clock controller (GCC)Stephen Boyd3-0/+2703
2014-01-17clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)Stephen Boyd3-0/+2331
2014-01-17clk: qcom: Add support for MSM8960's global clock controller (GCC)Stephen Boyd3-0/+3003
2014-01-17clk: qcom: Add reset controller supportStephen Boyd4-1/+102
2014-01-17clk: qcom: Add support for branches/gate clocksStephen Boyd3-0/+216
2014-01-17clk: qcom: Add support for root clock generators (RCGs)Stephen Boyd4-0/+969
2014-01-17clk: qcom: Add support for phase locked loops (PLLs)Stephen Boyd3-0/+289
2014-01-17clk: qcom: Add a regmap type clock structStephen Boyd6-0/+170
2014-01-17clk: Add set_rate_and_parent() opStephen Boyd1-19/+59
2014-01-17clk: sirf: re-arch to make the codes support both prima2 and atlas6Barry Song7-172/+458
2014-01-15clk: composite: pass mux_hw into determine_rateMike Turquette1-1/+1
2014-01-14Merge branch 'clk-next-shmobile' into clk-nextMike Turquette1-4/+8
2014-01-14clk: shmobile: Fix MSTP clock array initializationValentine Barshak1-2/+6
2014-01-14clk: shmobile: Fix MSTP clock indexValentine Barshak1-2/+2
2014-01-09Merge tag 'for_3.14/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel...Mike Turquette5-1162/+1284
2014-01-08clk: max77686: Register OF clock providerTomasz Figa1-0/+24
2014-01-08clk: max77686: Refactor driver data handlingTomasz Figa1-13/+14
2014-01-08clk: max77686: Fix clean-up in error and remove pathsTomasz Figa1-19/+10
2014-01-08clk: max77686: Make max77686_clk_register() return struct clk *Tomasz Figa1-7/+10
2014-01-08clk: max77686: Refactor successful exit of probe functionTomasz Figa1-2/+1
2014-01-08clk: max77686: Provide .recalc_rate() operationTomasz Figa1-0/+7
2014-01-08clk: max77686: Correct callback used for checking clock statusTomasz Figa1-2/+2
2014-01-08clk: exynos-audss: add support for Exynos 5420Andrew Bresticker1-7/+33
2014-01-08clk: exynos5250: add clock ID for div_pcm0Andrew Bresticker1-1/+1
2014-01-08clk: exynos-audss: allow input clocks to be specified in device treeAndrew Bresticker1-5/+20
2014-01-08clk: exynos-audss: convert to platform deviceAndrew Bresticker1-16/+88
2014-01-08clk: exynos5440: replace clock ID private enums with IDs from DT headerAndrzej Hajda1-47/+34
2014-01-08clk: exynos5420: replace clock ID private enums with IDs from DT headerAndrzej Hajda1-339/+309
2014-01-08clk: exynos5250: replace clock ID private enums with IDs from DT headerAndrzej Hajda1-295/+264
2014-01-08clk: exynos4: replace clock ID private enums with IDs from DT headerAndrzej Hajda1-455/+402
2014-01-08clk: exynos5250: register APLL rate tableAndrew Bresticker1-1/+24
2013-12-31Merge branch 'clk-next-unregister' into clk-nextMike Turquette3-13/+200
2013-12-30Merge branch 'for_3.14/keystone-clk' of git://git.kernel.org/pub/scm/linux/ke...Mike Turquette2-8/+28
2013-12-30clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apllSachin Kamat1-1/+2
2013-12-30clk: samsung: exynos5250: Fix parents of gate clocks from MFC domainTomasz Figa1-3/+5
2013-12-30clk: samsung: exynos5250: Correct parent list of audio muxesTomasz Figa1-3/+3
2013-12-30clk: samsung: exynos5250: Add missing unpopulated mux parentsTomasz Figa1-4/+12
2013-12-30clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domainTomasz Figa1-6/+8
2013-12-30clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domainTomasz Figa1-8/+17
2013-12-30clk: samsung: exynos5250: Make names of mux and div clocks consistentTomasz Figa1-122/+123