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path: root/drivers/clk/uniphier/clk-uniphier-sys.c
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2017-12-14clk: uniphier: fix DAPLL2 clock rate of Pro5Masahiro Yamada1-1/+1
[ Upstream commit 67affb78a4e4feb837953e3434c8402a5c3b272f ] The parent of DAPLL2 should be DAPLL1. Fix the clock connection. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-10-24clk: uniphier: fix clock data for PXs3Masahiro Yamada1-3/+3
Fix reg offsets of USB clocks. Fixes: 736de651a836 ("clk: uniphier: add PXs3 clock data") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01clk: uniphier: add video input subsystem clockKatsuhiro Suzuki1-0/+6
Add a clock for video input subsystem (EXIV) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01clk: uniphier: add audio system clockKatsuhiro Suzuki1-0/+12
Add clock for audio subsystem (AIO) and SoC internal audio codec (EVEA) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01clk: uniphier: add PXs3 clock dataMasahiro Yamada1-0/+30
Add basic clock data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31clk: uniphier: add ethernet clock control supportKunihiko Hayashi1-0/+10
Add clock control for ethernet controller on Pro4, PXs2, LD11 and LD20. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-04clk: uniphier: remove sLD3 SoC supportMasahiro Yamada1-28/+14
This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: uniphier: provide NAND controller clock rateMasahiro Yamada1-4/+11
This allows the NAND driver to get the clock rate via clk_get_rate(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-03clk: uniphier: add eMMC clock for LD11 and LD20 SoCsMasahiro Yamada1-0/+7
Add clock for the Cadence eMMC controller on LD11/LD20. For the other SoCs, the clock for the eMMC controller is included in the MIO/SD control block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-03clk: uniphier: add NAND clock for all UniPhier SoCsMasahiro Yamada1-0/+14
Add clock line for the Denali NAND controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: uniphier: add cpufreq data for LD11, LD20 SoCsMasahiro Yamada1-0/+32
Add more data to 64bit SoCs for the cpufreq support. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-17clk: uniphier: add clock data for UniPhier SoCsMasahiro Yamada1-0/+151
Add clock data arrays for all UniPhier SoCs with a binding document. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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