kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-03-12	clk: tegra: Fix pll_u rate configuration	Marcel Ziswiler	1	-0/+2
2018-03-12	clk: tegra: Specify VDE clock rate	Dmitry Osipenko	4	-1/+4
2018-03-12	clk: tegra20: Correct PLL_C_OUT1 setup	Dmitry Osipenko	1	-3/+3
2018-03-12	clk: tegra: Mark HCLK, SCLK and EMC as critical	Dmitry Osipenko	8	-36/+26
2018-03-08	clk: tegra: MBIST work around for Tegra210	Peter De Schrijver	1	-2/+342
2018-03-08	clk: tegra: add fence_delay for clock registers	Peter De Schrijver	1	-0/+7
2018-03-08	clk: tegra: Add la clock for Tegra210	Peter De Schrijver	1	-0/+14
2017-11-18	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	13	-66/+102
2017-11-02	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	Greg Kroah-Hartman	2	-0/+2
2017-11-01	clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()	Nicolin Chen	1	-2/+2
2017-11-01	clk: tegra: dfll: Fix drvdata overwriting issue	Nicolin Chen	3	-13/+11
2017-11-01	clk: tegra: Fix cclk_lp divisor register	Michał Mirosław	1	-1/+1
2017-11-01	clk: tegra: Bump SCLK clock rate to 216 MHz	Dmitry Osipenko	1	-1/+1
2017-11-01	clk: tegra: Use common definition of APBDMA clock gate	Dmitry Osipenko	1	-5/+1
2017-11-01	clk: tegra: Correct parent of the APBDMA clock	Dmitry Osipenko	1	-1/+1
2017-11-01	clk: tegra: Add AHB DMA clock entry	Dmitry Osipenko	4	-0/+4
2017-11-01	clk: tegra: Mark APB clock as critical	Jon Hunter	1	-1/+1
2017-10-19	clk: tegra: Make tegra_clk_pll_params __ro_after_init	Bhumika Goyal	1	-8/+8
2017-10-19	clk: tegra: Fix sor1_out clock implementation	Thierry Reding	2	-16/+47
2017-10-19	clk: tegra: Use tegra_clk_register_periph_data()	Thierry Reding	4	-13/+4
2017-10-19	clk: tegra: Add peripheral clock registration helper	Thierry Reding	2	-0/+11
2017-10-19	clk: tegra: Check BPMP response return code	Timo Alho	1	-5/+10
2017-08-24	clk: tegra: Fix Tegra210 PLLU initialization	Alex Frid	1	-2/+4
2017-08-24	clk: tegra: Correct Tegra210 UTMIPLL poweron delay	Alex Frid	1	-3/+3
2017-08-24	clk: tegra: Fix T210 PLLRE registration	Alex Frid	1	-20/+1
2017-08-24	clk: tegra: Update T210 PLLSS (D2/DP) registration	Alex Frid	1	-39/+9
2017-08-24	clk: tegra: Re-factor T210 PLLX registration	Alex Frid	4	-49/+10
2017-08-24	clk: tegra: don't warn for pll_d2 defaults unnecessarily	Peter De Schrijver	1	-2/+4
2017-08-24	clk: tegra: change post IDDQ release delay to 5us	Peter De Schrijver	1	-1/+1
2017-08-24	clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C	Alex Frid	1	-1/+2
2017-08-24	clk: tegra: Fix T210 effective NDIV calculation	Alex Frid	1	-4/+5
2017-08-24	clk: tegra: Init cfg structure in _get_pll_mnp	Peter De Schrijver	1	-0/+2
2017-08-24	clk: tegra210: remove non-existing VFIR clock	Peter De Schrijver	1	-1/+0
2017-08-24	clk: tegra: disable SSC for PLL_D2	Peter De Schrijver	1	-1/+1
2017-08-24	clk: tegra: Enable PLL_SS for Tegra210	Peter De Schrijver	1	-1/+1
2017-08-24	clk: tegra: fix SS control on PLL enable/disable	Peter De Schrijver	1	-20/+24
2017-07-22	clk: Convert to using %pOF instead of full_name	Rob Herring	1	-7/+5
2017-04-04	clk: tegra: Don't reset PLL-CX if it is already enabled	Jon Hunter	1	-4/+4
2017-04-04	clk: tegra: Add missing Tegra210 clocks	Peter De Schrijver	3	-0/+19
2017-04-04	clk: tegra: Propagate clk_out_x rate to parent	Alex Frid	1	-2/+4
2017-03-20	clk: tegra: Fix build warnings on Tegra20/Tegra30	Thierry Reding	2	-2/+2
2017-03-20	clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on	Peter De Schrijver	1	-0/+2
2017-03-20	clk: tegra: Add SATA seq input control	Peter De Schrijver	1	-0/+25
2017-03-20	clk: tegra: Add Tegra210 special resets	Peter De Schrijver	1	-0/+85
2017-03-20	clk: tegra: Rework pll_u	Peter De Schrijver	2	-197/+272
2017-03-20	clk: tegra: Implement reset control reset	Mikko Perttunen	1	-0/+16
2017-03-20	clk: tegra: Fix disable unused for clocks sharing enable bit	Peter De Schrijver	1	-0/+3
2017-03-20	clk: tegra: Handle UTMIPLL IDDQ	Peter De Schrijver	1	-0/+26
2017-03-20	clk: tegra: Add aclk	Peter De Schrijver	1	-0/+10
2017-03-20	clk: tegra: Add super clock mux/divider	Peter De Schrijver	2	-5/+89