index
:
kernel/linux.git
linux-2.6.11.y
linux-2.6.12.y
linux-2.6.13.y
linux-2.6.14.y
linux-2.6.15.y
linux-2.6.16.y
linux-2.6.17.y
linux-2.6.18.y
linux-2.6.19.y
linux-2.6.20.y
linux-2.6.21.y
linux-2.6.22.y
linux-2.6.23.y
linux-2.6.24.y
linux-2.6.25.y
linux-2.6.26.y
linux-2.6.27.y
linux-2.6.28.y
linux-2.6.29.y
linux-2.6.30.y
linux-2.6.31.y
linux-2.6.32.y
linux-2.6.33.y
linux-2.6.34.y
linux-2.6.35.y
linux-2.6.36.y
linux-2.6.37.y
linux-2.6.38.y
linux-2.6.39.y
linux-3.0.y
linux-3.1.y
linux-3.10.y
linux-3.11.y
linux-3.12.y
linux-3.13.y
linux-3.14.y
linux-3.15.y
linux-3.16.y
linux-3.17.y
linux-3.18.y
linux-3.19.y
linux-3.2.y
linux-3.3.y
linux-3.4.y
linux-3.5.y
linux-3.6.y
linux-3.7.y
linux-3.8.y
linux-3.9.y
linux-4.0.y
linux-4.1.y
linux-4.10.y
linux-4.11.y
linux-4.12.y
linux-4.13.y
linux-4.14.y
linux-4.15.y
linux-4.16.y
linux-4.17.y
linux-4.18.y
linux-4.19.y
linux-4.2.y
linux-4.20.y
linux-4.3.y
linux-4.4.y
linux-4.5.y
linux-4.6.y
linux-4.7.y
linux-4.8.y
linux-4.9.y
linux-5.0.y
linux-5.1.y
linux-5.10.y
linux-5.11.y
linux-5.12.y
linux-5.13.y
linux-5.14.y
linux-5.15.y
linux-5.16.y
linux-5.17.y
linux-5.18.y
linux-5.19.y
linux-5.2.y
linux-5.3.y
linux-5.4.y
linux-5.5.y
linux-5.6.y
linux-5.7.y
linux-5.8.y
linux-5.9.y
linux-6.0.y
linux-6.1.y
linux-6.10.y
linux-6.11.y
linux-6.12.y
linux-6.2.y
linux-6.3.y
linux-6.4.y
linux-6.5.y
linux-6.6.y
linux-6.7.y
linux-6.8.y
linux-6.9.y
linux-rockchip-6.1.y
linux-rockchip-6.5.y
linux-rolling-lts
linux-rolling-stable
master
Linux kernel stable tree (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
clk
/
tegra
/
clk.h
Age
Commit message (
Expand
)
Author
Files
Lines
2017-10-19
clk: tegra: Add peripheral clock registration helper
Thierry Reding
1
-0
/
+3
2017-08-24
clk: tegra: Re-factor T210 PLLX registration
Alex Frid
1
-6
/
+0
2017-03-20
clk: tegra: Fix build warnings on Tegra20/Tegra30
Thierry Reding
1
-1
/
+1
2017-03-20
clk: tegra: Add super clock mux/divider
Peter De Schrijver
1
-1
/
+6
2017-03-20
clk: tegra: Fix constness for peripheral clocks
Peter De Schrijver
1
-2
/
+2
2017-03-20
clk: tegra: Fix type for m field
Peter De Schrijver
1
-1
/
+1
2016-06-30
clk: tegra: Initialize UTMI PLL when enabling PLLU
Andrew Bresticker
1
-0
/
+17
2016-04-28
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Rhyland Klein
1
-0
/
+6
2016-04-28
clk: tegra: Add fixed factor peripheral clock type
Thierry Reding
1
-0
/
+17
2016-04-28
clk: tegra: Constify peripheral clock registers
Thierry Reding
1
-2
/
+2
2015-12-17
clk: tegra: Add support for Tegra210 clocks
Rhyland Klein
1
-0
/
+3
2015-12-17
clk: tegra: Add Super Gen5 Logic
Bill Huang
1
-0
/
+3
2015-12-17
clk: tegra: pll: Add logic for SS
Bill Huang
1
-0
/
+4
2015-12-17
clk: tegra: pll: Add dyn_ramp callback
Rhyland Klein
1
-0
/
+4
2015-12-17
clk: tegra: pll: Add Set_default logic
Bill Huang
1
-0
/
+11
2015-12-17
clk: tegra: pll: Adjust vco_min if SDM present
Bill Huang
1
-0
/
+4
2015-12-17
clk: tegra: pll: Add support for PLLMB for Tegra210
Rhyland Klein
1
-0
/
+9
2015-12-17
clk: tegra: pll: Add specialized logic for Tegra210
Rhyland Klein
1
-0
/
+24
2015-11-20
clk: tegra: pll: Add code to handle if resets are supported by PLL
Bill Huang
1
-0
/
+4
2015-11-20
clk: tegra: pll: Add logic for out-of-table rates for T210
Rhyland Klein
1
-0
/
+13
2015-11-20
clk: tegra: pll: Add logic for handling SDM data
Rhyland Klein
1
-1
/
+14
2015-11-20
clk: tegra: pll: Change misc_reg count from 3 to 6
Bill Huang
1
-1
/
+3
2015-11-20
clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header
Rhyland Klein
1
-0
/
+1
2015-11-20
clk: tegra: Constify pdiv-to-hw mappings
Thierry Reding
1
-1
/
+1
2015-10-20
clk: tegra: Modify tegra_audio_clk_init to accept more plls
Rhyland Klein
1
-1
/
+17
2015-10-20
clk: tegra: Update struct tegra_clk_pll_params kerneldoc
Thierry Reding
1
-3
/
+15
2015-10-20
clk: tegra: Fix comments for structure definitions
Rhyland Klein
1
-37
/
+37
2015-07-16
clk: tegra: Introduce ability for SoC-specific reset control callbacks
Mikko Perttunen
1
-0
/
+3
2015-05-13
clk: tegra: EMC clock driver depends on EMC driver
Thierry Reding
1
-0
/
+9
2015-05-13
clk: tegra: Add EMC clock driver
Mikko Perttunen
1
-0
/
+3
2015-04-10
clk: tegra: Model oscillator as clock
Thierry Reding
1
-4
/
+4
2015-04-10
clk: tegra: Fix typo tabel -> table
Thierry Reding
1
-1
/
+1
2014-11-26
clk: tegra: Implement memory-controller clock
Thierry Reding
1
-0
/
+2
2013-12-12
clk: tegra: remove legacy reset APIs
Stephen Warren
1
-1
/
+0
2013-12-12
clk: tegra: implement a reset driver
Stephen Warren
1
-1
/
+1
2013-11-26
clk: tegra: add TEGRA_PERIPH_NO_GATE
Peter De Schrijver
1
-0
/
+1
2013-11-26
clk: tegra: add locking to periph clks
Peter De Schrijver
1
-4
/
+6
2013-11-26
clk: tegra: Add support for PLLSS
Peter De Schrijver
1
-0
/
+5
2013-11-26
clk: tegra: introduce common gen4 super clock
Peter De Schrijver
1
-0
/
+3
2013-11-26
clk: tegra: move PMC, fixed clocks to common files
Peter De Schrijver
1
-0
/
+7
2013-11-26
clk: tegra: move periph clocks to common file
Peter De Schrijver
1
-2
/
+9
2013-11-26
clk: tegra: move audio clk to common file
Peter De Schrijver
1
-0
/
+4
2013-11-26
clk: tegra: add clkdev registration infra
Peter De Schrijver
1
-0
/
+7
2013-11-26
clk: tegra: add common infra for DT clocks
Peter De Schrijver
1
-0
/
+7
2013-11-26
clk: tegra: move fields to tegra_clk_pll_params
Peter De Schrijver
1
-23
/
+11
2013-11-26
clk: tegra: Add TEGRA_PERIPH_NO_DIV flag
Peter De Schrijver
1
-0
/
+1
2013-11-26
clk: tegra: common periph_clk_enb_refcnt and clks
Peter De Schrijver
1
-7
/
+9
2013-11-26
clk: tegra: simplify periph clock data
Peter De Schrijver
1
-8
/
+9
2013-06-18
clk: tegra: T114: add DFLL DVCO reset control
Paul Walmsley
1
-0
/
+2
2013-06-18
clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
Paul Walmsley
1
-0
/
+4
[next]