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path: root/drivers/clk/tegra/clk-tegra30.c
AgeCommit message (Expand)AuthorFilesLines
2013-04-05clk: tegra: Add PLL post divider tablePeter De Schrijver1-0/+7
2013-04-05clk: tegra: Refactor PLL programming codePeter De Schrijver1-117/+117
2013-04-05clk: tegra: defer application of init tableStephen Warren1-1/+6
2013-04-05clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad1-1/+1
2013-04-05clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding1-0/+2
2013-03-30ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>Stephen Warren1-2/+1
2013-03-05clk: Tegra: Remove duplicate smp_twd clockPrashant Gaikwad1-1/+0
2013-02-13clk: tegra: initialise parent of uart clocksLaxman Dewangan1-1/+5
2013-02-13clk: tegra: fix driver to match DT bindingStephen Warren1-3/+3
2013-02-12clk: tegra: local arrays should be staticPeter De Schrijver1-10/+10
2013-02-12clk: tegra: Add missing spinlock for hclk and pclkPeter De Schrijver1-4/+7
2013-02-12clk: tegra: fix wrong clock index between se to sata_coldJoseph Lo1-3/+3
2013-01-28clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()sPrashant Gaikwad1-70/+0
2013-01-28clk: tegra: add clock support for Tegra30Prashant Gaikwad1-0/+2057