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path: root/drivers/clk/tegra/clk-tegra114.c
AgeCommit message (Expand)AuthorFilesLines
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang1-2/+8
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding1-1/+6
2014-06-25clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver1-1/+30
2014-05-23clk: tegra: Initialize xusb clocksAndrew Bresticker1-1/+6
2014-05-23clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker1-10/+5
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker1-4/+4
2013-12-12clk: tegra: implement a reset driverStephen Warren1-1/+2
2013-11-26clk: tegra: Initialize DSI low-power clocksThierry Reding1-0/+2
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot1-0/+1
2013-11-26clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen1-0/+2
2013-11-26clk: tegra: introduce common gen4 super clockPeter De Schrijver1-74/+2
2013-11-26clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver1-74/+1
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver1-574/+17
2013-11-26clk: tegra: move audio clk to common filePeter De Schrijver1-208/+182
2013-11-26clk: tegra: add clkdev registration infraPeter De Schrijver1-159/+163
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver1-31/+43
2013-11-26clk: tegra: use pll_ref as the pll_e parentPeter De Schrijver1-1/+2
2013-11-26clk: tegra: move some PLLC and PLLXC init to clk-pll.cPeter De Schrijver1-89/+20
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver1-41/+16
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver1-235/+141
2013-11-26clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3dThierry Reding1-4/+4
2013-11-26clk: tegra: Set the clk parent of host1x to pll_pAndrew Chew1-0/+1
2013-11-26clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver1-24/+29
2013-11-25clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2Mark Zhang1-0/+3
2013-11-25clk: tegra: Fix vde/2d/3d clock src offsetMark Zhang1-10/+3
2013-11-25clk: tegra: Correct sbc mux width & parentMark Zhang1-6/+6
2013-11-25clk: tegra: replace enum tegra114_clk by binding headerPeter De Schrijver1-233/+198
2013-09-10Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds1-13/+25
2013-08-19clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan1-12/+24
2013-08-12clk: tegra114: add LP1 suspend/resume supportJoseph Lo1-0/+12
2013-08-09clk: tegra114: Fix incorrect placement of __initdataSachin Kamat1-1/+1
2013-07-19clk: tegra: add suspend/resume function for tegra_cpu_car_opsJoseph Lo1-0/+26
2013-07-03Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds1-7/+263
2013-06-18clk: tegra: T114: add DFLL DVCO reset controlPaul Walmsley1-0/+37
2013-06-18clk: tegra: T114: add DFLL source clocksPaul Walmsley1-0/+11
2013-06-18clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLLPaul Walmsley1-0/+118
2013-06-12clk: tegra: override bits for Tegra114 PLLMPeter De Schrijver1-0/+9
2013-06-12clk: tegra: fix sclk_parentsPeter De Schrijver1-1/+1
2013-06-12clk: tegra: PLL m,n,p init for Tegra114Peter De Schrijver1-0/+77
2013-06-12clk: tegra: pllp_out2 divider is int onlyPeter De Schrijver1-2/+2
2013-06-05clk: tegra114: Fix msenc clock registerMikko Perttunen1-1/+1
2013-05-31clk: tegra: Use common of_clk_init functionPrashant Gaikwad1-1/+2
2013-05-31clk: tegra114: correctly output clk_32kAlexandre Courbot1-0/+3
2013-05-31clk: tegra: fix clk_out parents listPrashant Gaikwad1-2/+2
2013-05-23clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_opsJoseph Lo1-1/+22
2013-04-05clk: tegra: fix enum tegra114_clk to match bindingStephen Warren1-1/+1
2013-04-05clk: tegra: Remove forced clk_enable of uartdPeter De Schrijver1-1/+1
2013-04-05clk: tegra: Implement clocks for Tegra114Peter De Schrijver1-0/+2085