Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2015-02-02 | clk: tegra: Define PLLD_DSI and remove dsia(b)_mux | Mark Zhang | 1 | -2/+0 |
2015-02-02 | clk: tegra: SDMMC controllers are on APB | Andrew Bresticker | 1 | -8/+8 |
2014-06-25 | clk: tegra: fix vi_sensor clocks on Tegra124 | Peter De Schrijver | 1 | -2/+2 |
2014-05-23 | clk: tegra: Fix xusb_hs_src clock hierarchy | Andrew Bresticker | 1 | -0/+6 |
2014-05-23 | clk: tegra: Fix xusb_fs_src mux | Jim Lin | 1 | -1/+3 |
2014-02-20 | clk: tegra: Fix vic03 mux index | Peter De Schrijver | 1 | -3/+1 |
2014-02-17 | clk: tegra: fix sdmmc clks on Tegra1x4 | Andrew Bresticker | 1 | -0/+4 |
2014-02-17 | clk: tegra: Correct clock number for UARTE | Thierry Reding | 1 | -1/+1 |
2013-11-26 | clk: tegra124: Add new peripheral clocks | Peter De Schrijver | 1 | -0/+69 |
2013-11-26 | clk: tegra: add TEGRA_PERIPH_NO_GATE | Peter De Schrijver | 1 | -0/+6 |
2013-11-26 | clk: tegra: add locking to periph clks | Peter De Schrijver | 1 | -15/+18 |
2013-11-26 | clk: tegra: move periph clocks to common file | Peter De Schrijver | 1 | -0/+596 |