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path: root/drivers/clk/tegra/clk-id.h
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2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang1-2/+0
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
2014-05-23clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker1-0/+1
Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker1-0/+4
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2013-11-26clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver1-0/+22
Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: add header for common tegra clock IDsPeter De Schrijver1-0/+213
Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>