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path: root/drivers/clk/sunxi
AgeCommit message (Expand)AuthorFilesLines
2015-08-25clk: sunxi: Convert to clk_hw based provider APIsStephen Boyd3-14/+14
2015-08-25clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd2-2/+2
2015-08-25clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()Stephen Boyd3-3/+3
2015-08-12clk: sunxi: Add a simple gates driverMaxime Ripard3-177/+159
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd6-5/+10
2015-07-28clk: sunxi: make use of of_clk_parent_fill helper functionDinh Nguyen4-19/+7
2015-07-28clk: fix some determine_rate implementationsBoris Brezillon3-4/+11
2015-07-28clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon3-33/+29
2015-07-20clk: sunxi: Include clk.h and remove unused clkdev.h includesStephen Boyd6-5/+10
2015-07-02Merge tag 'module-builtin_driver-v4.1-rc8' of git://git.kernel.org/pub/scm/li...Linus Torvalds1-1/+1
2015-06-16drivers/clk: convert sunxi/clk-mod0.c to use builtin_platform_driverPaul Gortmaker1-1/+1
2015-06-02clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCsHans de Goede1-0/+11
2015-05-05clk: sunxi: Fix of_io_request_and_map error checkMaxime Ripard2-5/+7
2015-03-25clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6Chen-Yu Tsai1-1/+2
2015-03-25clk: sunxi: Make divs clocks specify which output is the base factor clockChen-Yu Tsai1-12/+25
2015-03-21clk: sunxi: Register divs clocks before factor clocksChen-Yu Tsai1-3/+3
2015-03-21clk: sunxi: Add "cpu" to list of protected clocks for sun5iChen-Yu Tsai1-0/+1
2015-03-21clk: sunxi: Add muxable ahb factors clock for sun5i and sun7iChen-Yu Tsai1-0/+52
2015-02-23clk: sunxi: Add support for sun9i A80 USB clocks and resetsChen-Yu Tsai1-0/+43
2015-02-23clk: sunxi: Move USB clocks to separate fileChen-Yu Tsai3-88/+191
2015-02-21Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds9-143/+716
2015-02-03clk: Add rate constraints to clocksTomeu Vizoso3-0/+6
2015-01-25sunxi: clk: Set sun6i-pll1 n_start = 1Hans de Goede1-0/+1
2015-01-25clk: sunxi: rewrite sun9i_a80_get_pll4_factors()Hans de Goede1-28/+29
2015-01-20clk: sunxi: Add driver for A80 MMC config clocks/resetsChen-Yu Tsai2-0/+220
2015-01-20clk: sunxi: Add mod0 and mmc module clock support for A80Chen-Yu Tsai1-0/+32
2015-01-14clk: sunxi: Add a common setup function for mmc module clocksChen-Yu Tsai1-7/+19
2015-01-14clk: sunxi: Remove custom phase functionMaxime Ripard1-37/+0
2015-01-14clk: sunxi: Rework MMC phase clocksMaxime Ripard1-62/+69
2015-01-06clk: sunxi: Propagate rate changes to parent for mux clocksChen-Yu Tsai1-1/+1
2015-01-06clk: sunxi: Make the mod0 clk driver also a platform driverHans de Goede1-3/+40
2015-01-05ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxiHans de Goede1-0/+1
2014-12-22clk: sunxi: Fix factor clocks usage for sun9i core clocksChen-Yu Tsai1-6/+56
2014-12-22clk: sunxi: Give sunxi_factors_register a registers parameterHans de Goede5-14/+51
2014-12-22clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai1-0/+208
2014-12-22clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks listChen-Yu Tsai1-1/+0
2014-12-04clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso2-4/+4
2014-11-23clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT muxHans de Goede1-1/+6
2014-11-23clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai1-12/+16
2014-11-23clk: sunxi: Specify number of child clocks for divs clocksChen-Yu Tsai1-2/+9
2014-11-23clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai1-7/+0
2014-11-11clk: sunxi: unify APB1 clockEmilio López1-5/+2
2014-10-21clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai1-0/+31
2014-10-21clk: sunxi: Add support for A80 basic bus clocksChen-Yu Tsai2-0/+272
2014-10-21clk: sunxi: make factors clock mux mask configurableChen-Yu Tsai5-3/+5
2014-09-27Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kerne...Mike Turquette6-156/+485
2014-09-27clk: sunxi: Add sun8i MBUS clock supportChen-Yu Tsai2-0/+79
2014-09-27clk: sunxi: mod0: Introduce MMC proper phase handlingMaxime Ripard1-0/+189
2014-09-27clk: sunxi: Move mbus to mod0 fileMaxime Ripard2-57/+12
2014-09-27clk: sunxi: Move mod0 clock to a file of its ownMaxime Ripard3-1/+83