Age | Commit message (Expand) | Author | Files | Lines |
2018-03-21 | clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU | Icenowy Zheng | 2 | -1/+5 |
2018-03-18 | clk: sunxi-ng: add support for the Allwinner H6 CCU | Icenowy Zheng | 4 | -0/+1269 |
2018-03-18 | clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks | Icenowy Zheng | 2 | -3/+19 |
2018-03-02 | clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO | Jernej Skrabec | 1 | -1/+3 |
2018-03-02 | clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate | Jernej Skrabec | 1 | -3/+6 |
2018-03-02 | clk: sunxi-ng: h3: h5: Add minimal rate for video PLL | Jernej Skrabec | 1 | -11/+12 |
2018-03-02 | clk: sunxi-ng: Add check for minimal rate to NM PLLs | Jernej Skrabec | 2 | -0/+34 |
2018-02-15 | clk: sunxi-ng: Use u64 for calculation of nkmp rate | Jernej Skrabec | 1 | -3/+18 |
2018-02-15 | clk: sunxi-ng: Mask nkmp factors when setting register | Jernej Skrabec | 1 | -9/+12 |
2018-02-13 | clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name | Corentin Labbe | 1 | -7/+0 |
2018-01-27 | Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and 'clk-allwinner... | Stephen Boyd | 7 | -43/+185 |
2018-01-27 | Merge branch 'clk-divider-container' into clk-next | Stephen Boyd | 1 | -1/+1 |
2018-01-03 | clk: sunxi-ng: a83t: Add M divider to TCON1 clock | Jernej Škrabec | 1 | -2/+2 |
2017-12-29 | clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU | Icenowy Zheng | 1 | -3/+3 |
2017-12-29 | clk: sunxi-ng: add support for Allwinner H3 DE2 CCU | Icenowy Zheng | 1 | -0/+47 |
2017-12-29 | clk: divider: fix incorrect usage of container_of | Jerome Brunet | 1 | -1/+1 |
2017-12-22 | clk: move clock common macros out from vendor directories | Chunyan Zhang | 1 | -29/+0 |
2017-12-08 | clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL | Chen-Yu Tsai | 1 | -1/+10 |
2017-12-08 | clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL | Chen-Yu Tsai | 1 | -3/+6 |
2017-12-08 | clk: sunxi-ng: Support fixed post-dividers on NM style clocks | Chen-Yu Tsai | 2 | -13/+39 |
2017-12-07 | clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks | Chen-Yu Tsai | 1 | -20/+37 |
2017-12-07 | clk: sunxi-ng: Support fixed post-dividers on MP style clocks | Chen-Yu Tsai | 2 | -2/+42 |
2017-11-18 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 16 | -79/+453 |
2017-11-15 | clk: sunxi-ng: a83t: Fix i2c buses bits | Mylene JOSSERAND | 1 | -2/+2 |
2017-11-02 | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | Greg Kroah-Hartman | 3 | -0/+3 |
2017-10-17 | clk: sunxi-ng: sun4i: Export video PLLs | Jonathan Liu | 1 | -2/+2 |
2017-10-17 | clk: sunxi-ng: Add A83T display clocks | Maxime Ripard | 1 | -8/+13 |
2017-10-13 | clk: sunxi-ng: sun8i: a23: Use sigma-delta modulation for audio PLL | Chen-Yu Tsai | 1 | -13/+25 |
2017-10-13 | clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL | Chen-Yu Tsai | 1 | -13/+25 |
2017-10-13 | clk: sunxi-ng: sun5i: Use sigma-delta modulation for audio PLL | Chen-Yu Tsai | 1 | -6/+19 |
2017-10-13 | clk: sunxi-ng: sun4i: Use sigma-delta modulation for audio PLL | Chen-Yu Tsai | 1 | -6/+20 |
2017-10-13 | clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLL | Chen-Yu Tsai | 1 | -13/+25 |
2017-10-13 | clk: sunxi-ng: nm: Add support for sigma-delta modulation | Chen-Yu Tsai | 2 | -1/+46 |
2017-10-13 | clk: sunxi-ng: Add sigma-delta modulation support | Chen-Yu Tsai | 4 | -0/+240 |
2017-10-13 | clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock | Chen-Yu Tsai | 1 | -0/+3 |
2017-10-13 | clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider | Chen-Yu Tsai | 1 | -2/+2 |
2017-10-09 | clk: sunxi-ng: a83t: Fix invalid csi-mclk mux offset | Ondrej Jirman | 1 | -1/+1 |
2017-09-29 | clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision | Chen-Yu Tsai | 1 | -1/+1 |
2017-09-29 | clk: sunxi-ng: sun6i: Export video PLLs | Chen-Yu Tsai | 1 | -2/+6 |
2017-09-26 | clk: sunxi-ng: Implement reset control status readback | Chen-Yu Tsai | 1 | -0/+14 |
2017-09-17 | clk: sunxi-ng: Fix missing CLK_SET_RATE_PARENT in ccu-sun4i-a10.c | Alexander Syring | 1 | -1/+1 |
2017-09-17 | clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock | Icenowy Zheng | 1 | -1/+1 |
2017-09-17 | clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs | Icenowy Zheng | 1 | -9/+9 |
2017-09-13 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 22 | -36/+2990 |
2017-08-31 | Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kern... | Stephen Boyd | 4 | -0/+1531 |
2017-08-30 | clk: sunxi-ng: Provide a default reset hook | Maxime Ripard | 1 | -0/+12 |
2017-08-30 | clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock | Chen-Yu Tsai | 1 | -8/+2 |
2017-08-30 | clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes switching | Chen-Yu Tsai | 2 | -0/+110 |
2017-08-30 | clk: sunxi-ng: Add interface to query or configure MMC timing modes. | Chen-Yu Tsai | 3 | -0/+75 |
2017-08-24 | clk: sunxi-ng: Add sun4i/sun7i CCU driver | Priit Laes | 4 | -0/+1531 |