Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2016-09-17 | clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk | Chen-Yu Tsai | 1 | -1/+1 |
2016-09-17 | clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs | Chen-Yu Tsai | 1 | -10/+10 |
2016-09-17 | clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks | Chen-Yu Tsai | 1 | -9/+13 |
2016-08-25 | clk: sunxi-ng: Add A31/A31s clocks | Chen-Yu Tsai | 1 | -0/+1235 |