Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2017-12-22 | clk: sprd: add clocks support for SC9860 | Chunyan Zhang | 1 | -0/+3 |
2017-12-22 | clk: sprd: add adjustable pll support | Chunyan Zhang | 1 | -0/+1 |
2017-12-22 | clk: sprd: add composite clock support | Chunyan Zhang | 1 | -0/+1 |
2017-12-22 | clk: sprd: add divider clock support | Chunyan Zhang | 1 | -0/+1 |
2017-12-22 | clk: sprd: add mux clock support | Chunyan Zhang | 1 | -0/+1 |
2017-12-22 | clk: sprd: add gate clock support | Chunyan Zhang | 1 | -0/+1 |
2017-12-22 | clk: sprd: Add common infrastructure | Chunyan Zhang | 1 | -0/+3 |