Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2012-06-26 | clk: SPEAr600: Fix ethernet clock name for DT based probing | Stefan Roese | 1 | -1/+1 |
2012-06-21 | Viresh has moved | Viresh Kumar | 10 | -10/+10 |
2012-05-14 | SPEAr13xx: Add common clock framework support | Viresh Kumar | 3 | -0/+2072 |
2012-05-12 | SPEAr: Switch to common clock framework | Viresh Kumar | 3 | -0/+957 |
2012-05-12 | SPEAr: clk: Add General Purpose Timer Synthesizer clock | Viresh Kumar | 3 | -1/+172 |
2012-05-12 | SPEAr: clk: Add Fractional Synthesizer clock | Viresh Kumar | 3 | -1/+182 |
2012-05-12 | SPEAr: clk: Add Auxiliary Synthesizer clock | Viresh Kumar | 3 | -1/+242 |
2012-05-12 | SPEAr: clk: Add VCO-PLL Synthesizer clock | Viresh Kumar | 4 | -0/+462 |