Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-05-27 | clk: socfpga: stratix10: use new parent data scheme | Dinh Nguyen | 1 | -29/+131 |
2020-02-13 | clk: socfpga: stratix10: simplify parameter passing | Dinh Nguyen | 1 | -25/+4 |
2019-06-26 | clk: socfpga: stratix10: fix divider entry for the emac clocks | Dinh Nguyen | 1 | -2/+2 |
2019-06-26 | clk: socfpga: stratix10: add additional clocks needed for the NAND IP | Dinh Nguyen | 1 | -1/+5 |
2019-01-15 | clk: socfpga: stratix10: fix naming convention for the fixed-clocks | Dinh Nguyen | 1 | -10/+10 |
2018-07-06 | clk: socfpga: stratix10: fix the sdmmc_free_clk mux | Dinh Nguyen | 1 | -1/+1 |
2018-07-06 | clk: socfpga: stratix10: fix the parents of mpu_free_clk | Dinh Nguyen | 1 | -1/+6 |
2018-05-16 | clk: socfpga: stratix10: suppress unbinding platform's clock driver | Dinh Nguyen | 1 | -0/+1 |
2018-05-16 | clk: socfpga: stratix10: use platform driver APIs | Dinh Nguyen | 1 | -22/+17 |
2018-04-06 | clk: socfpga: stratix10: add clock driver for Stratix10 platform | Dinh Nguyen | 1 | -0/+345 |