summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas
AgeCommit message (Collapse)AuthorFilesLines
2025-04-08clk: renesas: r9a09g057: Add clock and reset entries for GE3DLad Prabhakar2-0/+16
Add PLLGPU along with the necessary clock and reset entries for GE3D. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-08clk: renesas: rzv2h: Rename PLL field macros for consistencyLad Prabhakar1-7/+7
Rename PLL field extraction macros to include the associated register name (`CPG_PLL_CLK1` or `CPG_PLL_CLK2`) to maintain consistency with other PLL register macros. Update all corresponding macro references accordingly. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-08clk: renesas: rzv2h: Add support for enabling PLLsLad Prabhakar1-0/+56
Some RZ/V2H(P) SoC variants do not have a GPU, resulting in PLLGPU being disabled by default in TF-A. Add support for enabling PLL clocks in the RZ/V2H(P) CPG driver to manage this. Introduce `is_enabled` and `enable` callbacks to handle PLL state transitions. With the `enable` callback, PLLGPU will be turned ON only when the GPU node is enabled; otherwise, it will remain off. Define new macros for PLL standby and monitor registers to facilitate this process. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-08clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk`Lad Prabhakar1-2/+0
Remove the redundant `type` field from `struct pll_clk`, as it is not used in the PLL clock handling logic. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-08clk: renesas: rzv2h: Refactor PLL configuration handlingLad Prabhakar4-15/+32
Refactor PLL handling by introducing a `struct pll` to encapsulate PLL configuration parameters, ensuring consistency with the existing dynamic divider structure. Introduce the `PLL_PACK()` macro to simplify PLL structure initialization and update the `DEF_PLL()` macro to use the new `pll` structure. Modify relevant clock register functions to utilize the structured PLL data instead of raw configuration values. This refactoring improves code readability, maintainability, and alignment with the existing clock configuration approach. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-06clk: renesas: r9a09g047: Add clock and reset signals for the TSU IPJohn Madieu1-0/+3
Add required clocks and resets signals for the TSU IP available on the Renesas RZ/G3E SoC Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250227122453.30480-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-06clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1Biju Das1-6/+6
Avoid using the "- 1" for finding mstop_index in all functions accessing priv->mstop_count, by adjusting its pointer in rzv2h_cpg_probe(). While at it, drop the intermediate local variable index. Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Closes: https://lore.kernel.org/all/CAMuHMdX1gPNCFddg_DyK7Bv0BeFLOLi=5eteT_HhMH=Ph2wVvA@mail.gmail.com/ Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250222142009.41324-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-04clk: renesas: r7s9210: Distinguish clocks by clock typeGeert Uytterhoeven1-6/+4
When registering a clock, its type should be devised from the clock's type member, not from its id member. Merge the two checks for the main clock, to improve readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/7e61ea78e9919148e73867088ccbc3509364952e.1740126560.git.geert+renesas@glider.be
2025-03-04clk: renesas: rzg2l: Remove unneeded nullify checksGeert Uytterhoeven1-10/+0
RZ/G2L family clock drivers never had a need to nullify clocks. Remove the unneeded checks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/64702c33396dde2689b44d3e326aa1727ef1557a.1740126560.git.geert+renesas@glider.be
2025-03-04clk: renesas: cpg-mssr: Remove obsolete nullify checkGeert Uytterhoeven1-5/+0
All core clock nullify users and helpers were removed in commit b1dec4e78599a2ce ("clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*"), but the CPG/MSSR driver still checks for nullified core clocks. Remove the obsolete check. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/59ef3eccde0b0b63626480f27e77d5c68948ca98.1740126560.git.geert+renesas@glider.be
2025-03-04clk: renesas: r9a09g057: Add entries for the DMACsFabrizio Castro2-0/+26
Add clock and reset entries for the Renesas RZ/V2H(P) DMAC IPs. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250220150110.738619-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-20clk: renesas: r9a09g047: Add CANFD clocks and resetsBiju Das1-0/+10
Add CANFD clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250218105007.66358-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-20clk: renesas: r9a09g047: Add CRU0 clocks and resetsTommaso Merciai1-0/+24
Add support for CRU0 clocks and resets along with the corresponding divider. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250210114540.524790-2-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-18clk: renesas: rzv2h: Update error messageLad Prabhakar1-2/+2
Update the error message in `rzv2h_mod_clock_endisable()` to provide clearer debugging information. Instead of printing only the register address, include both the `GET_CLK_ON_OFFSET(reg)` offset and the corresponding `clk` name (`%pC`). This enhances readability and aids in debugging clock enable failures. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250211105603.195905-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-18clk: renesas: rzg2l: Update error messageLad Prabhakar1-2/+2
Update the error message in `rzg2l_mod_clock_endisable()` to provide clearer debugging information. Instead of printing only the register address, include both the `CLK_ON_R(reg)` offset and the corresponding `clk` name (`%pC`). This enhances readability and aids in debugging clock enable failures. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250211105603.195905-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a09g047: Add ICU clock/resetBiju Das1-0/+3
Add ICU clock and reset entries. Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250128104714.80807-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a07g043: Fix HP clock source for RZ/FiveLad Prabhakar1-0/+7
According to the Rev.1.20 hardware manual for the RZ/Five SoC, the clock source for HP is derived from PLL6 divided by 2. Correct the implementation by configuring HP as a fixed clock source instead of a MUX. The `CPG_PL6_ETH_SSEL' register, which is available on the RZ/G2UL SoC, is not present on the RZ/Five SoC, necessitating this change. Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Cc: stable@vger.kernel.org Reported-by: Hien Huynh <hien.huynh.px@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250127173159.34572-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a09g047: Add SDHI clocks/resetsBiju Das1-0/+31
Add SDHI[0-2] clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250126134616.37334-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779h0: Add VSPX clockNiklas Söderlund1-0/+1
Add the VSPX modules clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115175927.3714357-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779h0: Add FCPVX clockNiklas Söderlund1-0/+1
Add the FCPVX modules clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115175927.3714357-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a08g045: Check the source of the CPU PLL settingsClaudiu Beznea3-6/+22
On the RZ/G3S SoC, the CPU PLL settings can be set and retrieved through the CPG_PLL1_CLK1 and CPG_PLL1_CLK2 registers. However, these settings are applied only when CPG_PLL1_SETTING.SEL_PLL1 is set to 0. Otherwise, the CPU PLL operates at the default frequency of 1.1 GHz. Hence add support to the PLL driver for returning the 1.1 GHz frequency when the CPU PLL is configured with the default frequency. Fixes: 01eabef547e6 ("clk: renesas: rzg2l: Add support for RZ/G3S PLL") Fixes: de60a3ebe410 ("clk: renesas: Add minimal boot support for RZ/G3S SoC") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115142059.1833063-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a09g047: Add WDT clocks and resetsBiju Das1-0/+15
WDT0 reset is for CM33. Add WDT[1-3] clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115103858.104709-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779h0: Add ISP core clocksNiklas Söderlund1-0/+1
Add the ISP core module clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250114183005.2761213-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779g0: Add ISP core clocksNiklas Söderlund1-0/+2
Add the ISP core modules clock for Renesas R-Car V4H. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250114183005.2761213-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779a0: Add ISP core clocksNiklas Söderlund1-0/+4
Add the ISP core modules clock for Renesas R-Car V3U. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250114183005.2761213-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779a0: Add FCPVX clocksNiklas Söderlund1-0/+4
Add the FCPVX modules clock for Renesas R-Car V3U. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250109125036.2399199-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a07g044: Add clock and reset entry for DRP-AILad Prabhakar2-2/+55
Add clock and reset entries for the DRP-AI block, which is available only on the Renesas RZ/V2L SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250106202853.262787-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ↵Claudiu Beznea1-0/+4
TSU IP Add clocks, resets and power domains for the TSU IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250103163805.1775705-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validationLad Prabhakar1-48/+54
Refactor rzg2l_cpg_attach_dev to delegate clock validation for Runtime PM to the updated rzg2l_cpg_is_pm_clk function. Ensure validation of clocks associated with the power domain while excluding external and core clocks. Prevent incorrect Runtime PM management for clocks outside the domain's scope. Update rzg2l_cpg_is_pm_clk to operate on a per-power-domain basis. Verify clkspec.np against the domain's device node, check argument validity, and validate clock type (CPG_MOD). Use the no_pm_mod_clks array to exclude specific clocks from PM management. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241216210201.239855-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g057: Add clock and reset entries for GICLad Prabhakar1-0/+4
Add clock and reset entries for GIC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250102181839.352599-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g057: Add reset entry for SYSLad Prabhakar1-0/+1
Add the missing reset entry for the `SYS` module in the clock driver. The corresponding core clock entry for `SYS` is already present. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250102181839.352599-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r8a779g0: Add VSPX clocksJacopo Mondi1-0/+2
Add the VSPX modules clock for Renesas R-Car V4H (R8A779G0) SoC. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com> Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-3-7dc1812585ad@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r8a779g0: Add FCPVX clocksJacopo Mondi1-0/+2
Add the FCPVX modules clock for Renesas R-Car V4H (R8A779G0) SoC. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com> Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-1-7dc1812585ad@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g047: Add I2C clocks/resetsBiju Das1-0/+32
Add I2C{0..8} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241216120029.143944-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g047: Add CA55 core clocksBiju Das1-0/+16
Add CA55 core clocks which are derived from PLLCA55. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/20241213123550.289193-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: rzv2h: Add support for RZ/G3E SoCBiju Das5-1/+116
The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1 are present only on the RZ/G3E SoC. Add minimal clock and reset entries required to boot the Renesas RZ/G3E SMARC EVK and binds it with the RZ/V2H CPG core driver. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/20241213123550.289193-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: rzv2h: Add MSTOP supportBiju Das3-79/+252
Add MSTOP support to control buses for the individual units on RZ/V2H. Use per-bit (instead of group-based) configuration and atomic counters, to ensure precise control over individual MSTOP bits, and to prevent issues with shared dependencies between module clocks. Co-developed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241213123550.289193-2-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-2-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-3-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-4-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ↵Claudiu Beznea1-0/+7
ADC IP Add clocks, resets and power domains for ADC IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/20241206111337.726244-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r8a779h0: Add display clocksTomi Valkeinen1-0/+4
Add display related clocks for DU, DSI, FCPVD, and VSPD. Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241206-rcar-gh-dsi-v3-5-d74c2166fa15@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resetsLad Prabhakar2-0/+51
Add support for the PLLVDO clock and its related CRU clocks and reset entries in the r9a09g057 CPG driver. Introduce `CLK_PLLVDO` and associated clocks like `CLK_PLLVDO_CRU0`, `CLK_PLLVDO_CRU1`, `CLK_PLLVDO_CRU2`, and `CLK_PLLVDO_CRU3`, along with their corresponding dividers. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241202203916.48668-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: rzv2h: Add selective Runtime PM support for clocksLad Prabhakar2-7/+49
Update `rzv2h_cpg_attach_dev` to prevent external and core clocks not tied to the power domain from being managed by Runtime PM. This ensures that only clocks originating from the domain are controlled, thereby avoiding unintended handling of external and core clocks. Additionally, introduce a `no_pm` flag in `mod_clock` and `rzv2h_mod_clk` structures to exclude specific clocks from Runtime PM when needed. Some clocks, such as those in the CRU block, require unique enable/disable sequences that are incompatible with standard Runtime PM. For example, the CSI-2 D-PHY clock initialization requires toggling individual clocks, making Runtime PM unsuitable. The helper function `rzv2h_cpg_is_pm_clk()` checks whether a clock should be managed by Runtime PM based on this `no_pm` flag. New macros, such as `DEF_MOD_NO_PM`, allow straightforward declaration of clocks that bypass PM. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241202203916.48668-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r9a06g032: Use BIT macro consistentlyWolfram Sang1-1/+1
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241128091113.24116-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r9a06g032: Add restart handlerWolfram Sang1-0/+27
The SYSCTRL module also does reset handling. Start supporting that by allowing software resets which can then be utilized by a restart handler. Finally 'reboot' will do something useful on RZ/N1D. Watchdog support to be added later. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241128091113.24116-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-03clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining ↵Claudiu Beznea1-0/+20
SCIFs The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug console and is already enabled. Add clock, reset and power domain support for the remaining ones. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241115134401.3893008-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-03clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSIClaudiu Beznea1-0/+20
Add SSI clocks, resets and power domains support for the SSI blocks available on the Renesas RZ/G3S SoC. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241113133540.2005850-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-03clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init()Javier Carrasco1-1/+1
A device_node reference obtained via of_find_node_by_path() requires explicit calls to of_node_put() after it is no longer required to avoid leaking the resource. Instead of adding the missing calls to of_node_put() in all execution paths, use the cleanup attribute for 'soc' by means of the __free() macro, which automatically calls of_node_put() when the variable goes out of scope. Fixes: 6aa175476490 ("clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system") Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241031-clk-renesas-cpg-mssr-cleanup-v2-1-0010936d1154@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-06clk: renesas: vbattb: Add VBATTB clock driverClaudiu Beznea3-0/+211
The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-03clk: renesas: rzg2l: Fix FOUTPOSTDIV clkBiju Das1-5/+6
While computing foutpostdiv_rate, the value of params->pl5_fracin is discarded, which results in the wrong refresh rate. Fix the formula for computing foutpostdiv_rate. Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support") Signed-off-by: Hien Huynh <hien.huynh.px@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241024134236.315289-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25clk: renesas: r9a08g045: Add power domain for RTCClaudiu Beznea1-0/+2
The RTC and VBATTB don't share the MSTOP control bit (but only the bus clock and the reset signal). As the MSTOP control is modeled though power domains add power domain support for the RTC device available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241019084738.3370489-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safeClaudiu Beznea1-2/+3
If the watchdog is part of a dedicated power domain (as it may be on RZ/G3S) the watchdog PM domain need to be powered on in the watchdog restart handler. Currently, only the clocks are enabled in the watchdog restart handler. To be able to also power on the PM domain we need to call pm_runtime_resume_and_get() on the watchdog restart handler, mark the watchdog device as IRQ safe and register the watchdog PM domain with GENPD_FLAG_IRQ_SAFE. Register watchdog PM domain as IRQ safe. Along with it the always-on PM domain (parent of the watchdog domain) was marked as IRQ safe. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/20241015164732.4085249-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-01 05:57:53 +0300