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2023-08-31Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and ↵Stephen Boyd17-19/+73
'clk-cleanup' into clk-next - Remove OXNAS clk driver * clk-bindings: dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml dt-bindings: clock: xlnx,versal-clk: drop select:false dt-bindings: clock: versal: Add versal-net compatible string dt-bindings: clock: ast2600: Add I3C and MAC reset definitions dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding * clk-starfive: reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support clk: starfive: Simplify .determine_rate() clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator * clk-rm: dt-bindings: clk: oxnas: remove obsolete bindings clk: oxnas: remove obsolete clock driver * clk-renesas: clk: renesas: rcar-gen3: Add ADG clocks clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock * clk-cleanup: clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() clk: Explicitly include correct DT includes
2023-08-15clk: renesas: rcar-gen3: Add ADG clocksKuninori Morimoto9-1/+9
R-Car Sound needs to enable "ADG" on RMSTPCR9/SMSTPCR9 bit 22 to use clk_i which came from the internal S0D4 or ZA2 clock. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> # R-Car M3-N Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> # R-Car M3-N Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87pm47prox.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87o7jrpros.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87mszbpron.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87leevproh.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87jzufprod.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87il9zpro8.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87h6pjpro4.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87fs53prny.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87edknprnt.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-27clk: renesas: r8a77965: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1767d01cfffd7490861f2cf6ad6c0df100916907.1689599217.git.geert+renesas@glider.be
2023-07-27clk: renesas: r8a7796: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/291462bea7ffc13f8218c1901dc384b576bfc2d6.1689599217.git.geert+renesas@glider.be
2023-07-27clk: renesas: r8a7795: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/36096e2df2a54516fadd1978c47fc7de354abc26.1689599217.git.geert+renesas@glider.be
2023-07-27clk: renesas: emev2: Remove obsolete clkdev registrationGeert Uytterhoeven1-3/+0
EMMA Mobile EV2 is a multi-platform/CCF-only platform, registering all devices from DT, so we can remove the registration of clkdevs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Niklas Söderlund <niklas.soderlund@ragnatech.se> Link: https://lore.kernel.org/r/f54a30d7a9e2aa075d462db701a60b0b59c6ad0b.1686325857.git.geert+renesas@glider.be
2023-07-25clk: renesas: r9a07g043: Add MTU3a clock and reset entryBiju Das1-0/+3
Add MTU3a clock and reset entry to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230714075649.146978-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-19clk: Explicitly include correct DT includesRob Herring3-4/+1
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-07-11clk: renesas: rzg2l: Simplify .determine_rate()Christophe JAILLET1-7/+1
rzg2l_cpg_sd_clk_mux_determine_rate() is the same as __clk_mux_determine_rate_closest(), so use the latter to save some LoC. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/fed02e0325275df84e2d76f8c481e40e7023cbd9.1688760372.git.christophe.jaillet@wanadoo.fr Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-10clk: renesas: r9a09g011: Add CSI related clocksFabrizio Castro1-0/+15
The Renesas RZ/V2M SoC comes with 6 CSI IPs (CSI0, CSI1, CSI2 CSI3, CSI4, and CSI5), however Linux is only allowed control of CSI0 and CSI4. CSI0 shares its reset and PCLK lines with CSI1, CSI2, and CSI3. CSI4 shares its reset and PCLK lines with CSI5. This commit adds support for the relevant clocks. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230622113341.657842-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-10clk: renesas: r8a774b1: Add 3DGE and ZG supportAdam Ford1-0/+2
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230617150302.38477-4-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-10clk: renesas: r8a774e1: Add 3DGE and ZG supportAdam Ford1-0/+2
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230617150302.38477-3-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-10clk: renesas: r8a774a1: Add 3DGE and ZG supportAdam Ford1-0/+2
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230617150302.38477-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-10clk: renesas: rcar-gen3: Add support for ZG clockAdam Ford2-4/+32
A clock used for the 3D graphics appears to be common among multiple SoC's, so add a generic gen3 clock for clocking the graphics. This is similar to the cpg_z_clk, with a different frequency control register and different flags. Instead of duplicating the code, make cpg_z_clk_register into a helper function and call the help function with the FCR and flags as a parameter. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230617150302.38477-1-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-06-26Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', ↵Stephen Boyd6-49/+27
'clk-samsung' and 'clk-amlogic' into clk-next - Make clk_ops::determine_rate mandatory for muxes * clk-renesas: clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic() clk: renesas: mstp: Convert to readl_poll_timeout_atomic() clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic() iopoll: Do not use timekeeping in read_poll_timeout_atomic() iopoll: Call cpu_relax() in busy loops clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write clk: renesas: r8a779a0: Add PWM clock * clk-determine-rate: (71 commits) clk: sprd: composite: Simplify determine_rate implementation ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_determine_rate() clk: Fix best_parent_rate after moving code into a separate function clk: Forbid to register a mux without determine_rate ASoC: tlv320aic32x4: div: Switch to determine_rate ASoC: tlv320aic32x4: pll: Switch to determine_rate clk: tegra: super: Switch to determine_rate clk: tegra: periph: Switch to determine_rate clk: stm32: composite: Switch to determine_rate clk: st: flexgen: Switch to determine_rate clk: sprd: composite: Switch to determine_rate clk: ingenic: tcu: Switch to determine_rate clk: ingenic: cgu: Switch to determine_rate clk: imx: scu: Switch to determine_rate clk: da8xx: clk48: Switch to determine_rate clk: si5351: clkout: Switch to determine_rate clk: si5351: msynth: Switch to determine_rate clk: si5351: pll: Switch to determine_rate clk: si5341: Switch to determine_rate clk: cdce706: clkout: Switch to determine_rate ... * clk-allwinner: clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux * clk-samsung: clk: samsung: add CONFIG_OF dependency clk: samsung: Re-add support for Exynos4212 CPU clock clk: samsung: Add Exynos4212 compatible to CLKOUT driver dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible * clk-amlogic: MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK clk: meson: pll: remove unneeded semicolon clk: meson: a1: Staticize rtc clk clk: meson: a1: add Amlogic A1 Peripherals clock controller driver clk: meson: a1: add Amlogic A1 PLL clock controller driver clk: meson: introduce new pll power-on sequence for A1 SoC family clk: meson: make pll rst bit as optional dt-bindings: clock: meson: add A1 Peripherals clock controller bindings dt-bindings: clock: meson: add A1 PLL clock controller bindings
2023-06-09clk: renesas: r9a06g032: Add a determine_rate hookMaxime Ripard1-0/+1
The Renesas r9a06g032 bitselect clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidates to trigger that parent change are either the assigned-clock-parents device tree property or a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. Similarly, it doesn't look like the device tree using that clock driver uses any of the assigned-clock properties on that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the determine_rate implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: linux-renesas-soc@vger.kernel.org Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-31-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-06-05clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven1-11/+5
Use readl_poll_timeout_atomic() instead of open-coding the same operation. As typically no retries are needed, 10 µs is a suitable timeout value. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/900543d4b9abc1004e6aecdb676f23e5508ae96f.1685692810.git.geert+renesas@glider.be
2023-06-05clk: renesas: mstp: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven1-11/+7
Use readl_poll_timeout_atomic() instead of open-coding the same operation. As typically no retries are needed, 10 µs is a suitable timeout value. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/bce7d0bdd80c800aa150f1868b610b7d94f4cc66.1685692810.git.geert+renesas@glider.be
2023-06-05clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven1-20/+11
Use readl_poll_timeout_atomic() instead of open-coding the same operation. As typically no retries are needed, 10 µs is a suitable timeout value. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/832d29fd9aa3239ea949535309d2bdb003d40c9e.1685692810.git.geert+renesas@glider.be
2023-05-23clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register writeBiju Das2-7/+2
As per the RZ/G2L HW(Rev.1.30 May2023) manual, there are no "write enable" bits in the CPG_SIPLL5_CLK1 register. So fix the CPG_SIPLL5_CLK register write by removing the "write enable" bits. Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230518152334.514922-1-biju.das.jz@bp.renesas.com [geert: Remove CPG_SIPLL5_CLK1_*_WEN bit definitions] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08clk: renesas: r8a779a0: Add PWM clockWolfram Sang1-0/+1
Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20230502170618.55967-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-04-30Merge tag 'clk-for-linus' of ↵Linus Torvalds7-204/+591
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Nothing looks out of the ordinary in this batch of clk driver updates. There are a couple patches to the core clk framework, but they're all basically cleanups or debugging aids. The driver updates and new additions are dominated in the diffstat by Qualcomm and MediaTek drivers. Qualcomm gained a handful of new drivers for various SoCs, and MediaTek gained a bunch of drivers for MT8188. The MediaTek drivers are being modernized as well, so there are updates all over that vendor's clk drivers. There's also a couple other new clk drivers in here, for example the Starfive JH7110 SoC support is added. Outside of the two major SoC vendors though, we have the usual collection of non-critical fixes and cleanups to various clk drivers. It's good to see that we're getting more cleanups and modernization patches. Maybe one day we'll be able to properly split clk providers from clk consumers. Core: - Print an informational message before disabling unused clks New Drivers: - BCM63268 timer clock and reset controller - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and MT8195 SoCs - Mediatek MT8188 SoC clk drivers - Clock driver for Sunplus SP7021 SoC - Clk driver support for Loongson-2 SoCs - Clock driver for Skyworks Si521xx I2C PCIe clock generators - Initial Starfive JH7110 clk/reset support - Global clock controller drivers for Qualcomm SM7150, IPQ9574, MSM8917 and IPQ5332 SoCs - GPU clock controller drivers for SM6115, SM6125, SM6375 and SA8775P SoCs Updates: - Shrink size of clk_fractional_divider a little - Convert various clk drivers to devm_of_clk_add_hw_provider() - Convert platform clk drivers to remove_new() - Converted most Mediatek clock drivers to struct platform_driver - MediaTek clock drivers can be built as modules - Reimplement Loongson-1 clk driver with DT support - Migrate socfpga clk driver to of_clk_add_hw_provider() - Support for i3c clks on Aspeed ast2600 SoCs - Add clock generic devm_clk_hw_register_gate_parent_data - Add audiomix block control for i.MX8MP - Add support for determine_rate to i.MX composite-8m - Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate - Provide clock name in error message for clk-gpr-mux on get parent failure - Drop duplicate imx_clk_mux_flags macro - Register the i.MX8MP Media Disp2 Pix clock as bus clock - Add Media LDB root clock to i.MX8MP - Make i.MX8MP nand_usdhc_bus clock as non-critical - Fix the rate table for i.MX fracn-gppll - Disable HW control for the fracn-gppll in order to be controlled by register write - Add support for interger PLL in fracn-gppll - Add mcore_booted module parameter to i.MX93 provider - Add NIC, A55 and ARM PLL clocks to i.MX93 - Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents - Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP to get more accurate clock rates - Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical - Update some of the i.MX critical clocks flags to allow glitchless on-the-fly rate change. - Add I2C5 clock on Renesas R-Car V3H - Exynos850: Add CMU_G3D clock controller for the Mali GPU - Extract Exynos5433 (ARM64) clock controller power management code to common driver parts - Exynos850: make PMU_ALIVE_PCLK clock critical - Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel Selector (ISPCS), and video capture (VIN) clocks on Renesas R-Car V4H - Add video capture (VIN) clocks on Renesas R-Car V3H - Add Cortex-A53 System CPU (Z2) clocks on Renesas R-Car V3M and V3H - Support for Stromer Plus PLL on Qualcomm IPQ5332 - Add a missing reset to Qualcomm QCM2290 - Migrate Qualcomm IPQ4019 to clk_parent_data - Make USB GDSCs enter retention state when disabled on Qualcomm SM6375, MSM8996 and MSM8998 SoCs - Set floor rounding clk_ops for Qualcomm QCM2290 SDCC2 clk - Add two EMAC GDSCs on Qualcomm SC8280XP - Use shared rcg clk ops in Qualcomm SM6115 GCC - Park Qualcomm SM8350 PCIe PIPE clks when disabled - Add GDSCs to Qualcomm SC7280 LPASS audio clock controller - Add missing XO clocks to Qualcomm MSM8226 and MSM8974 - Convert some Qualcomm clk DT bindings to YAML - Reparenting fix for the clock supplying camera modules on Rockchip rk3399 - Mark more critical (bus-)clocks on Rockchip rk3588" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (290 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers clk: rockchip: rk3588: make gate linked clocks critical clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: starfive: Avoid casting iomem pointers clk: microchip: fix potential UAF in auxdev release callback clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: mediatek: fhctl: Mark local variables static clk: sifive: make SiFive clk drivers depend on ARCH_ symbols clk: uniphier: Use managed `of_clk_add_hw_provider()` clk: si5351: Use managed `of_clk_add_hw_provider()` clk: si570: Use managed `of_clk_add_hw_provider()` clk: si514: Use managed `of_clk_add_hw_provider()` clk: lmk04832: Use managed `of_clk_add_hw_provider()` ...
2023-04-13clk: renesas: remove MODULE_LICENSE in non-modulesNick Alcock2-2/+0
Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock <nick.alcock@oracle.com> Suggested-by: Luis Chamberlain <mcgrof@kernel.org> Cc: Luis Chamberlain <mcgrof@kernel.org> Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa <hasegawa-hitomi@fujitsu.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-renesas-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
2023-03-30clk: renesas: r8a77980: Add I2C5 clockNikita Yushchenko1-0/+1
The MSSR clock definition for I2C5 was missing. Add it. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230328033902.830269-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-16clk: renesas: Convert to platform remove callback returning voidUwe Kleine-König1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230312161512.2715500-24-u.kleine-koenig@pengutronix.de Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10clk: renesas: r9a06g032: Improve clock tablesRalph Siemsen1-153/+407
Each entry in the clock table specifies a number of individual bits in registers, for contolling clock reset, gaiting, etc. These reg/bit were packed into a u16 to save space. The combined value is difficult to understand when reviewing the clock table entries. Introduce a "struct regbit" which still occupies only 16 bits, but allows the register and bit values to be specified explicitly. Convert all previous uses of u16 for reg/bit into "struct regbit". The bulk of this patch converts the clock table to use struct regbit, making use of the RB() helper macro. The conversion was automated by script, and as a further verification, the compiled binary of the table was compared before/after the change (with objdump -D). The clk_rdesc_set() function now checks for zero reg/bit internally. This allows callers of that function to remove those checks. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230301215520.828455-5-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10clk: renesas: r9a06g032: Document structsRalph Siemsen1-1/+49
Add some kerneldoc comments for the structures. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230301215520.828455-4-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10clk: renesas: r9a06g032: Drop unused fieldsRalph Siemsen1-5/+10
Drop three unused fields from the clock descriptor structure, and update the macros for filling such structures accordingly. The values for such fields are kept in the source code, now unused, in case they are needed later. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230301215520.828455-3-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10clk: renesas: r9a06g032: Improve readabilityRalph Siemsen1-41/+80
Several small readability improvements: - Move enum gate_type definition up and add comments to each field. - Use this enum instead of generic uint32_t type in clock desc struct. - Tidy up bitfield syntax and comments in clock desc structure - Reformat macros for building clock desc to have one assignment per line There is no functional change. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230301215520.828455-2-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10clk: renesas: r8a77980: Add Z2 clockGeert Uytterhoeven1-0/+1
Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3H, which uses a fixed SYS-CPU divider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/aad9eaa57acf65cbe43e4d374066a72d760d54d8.1676560357.git.geert+renesas@glider.be
2023-03-10clk: renesas: r8a77970: Add Z2 clockGeert Uytterhoeven1-0/+1
Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3M, which uses a fixed SYS-CPU divider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6a9169e5bc92c2b9549292769a0814e04b9147cf.1676560357.git.geert+renesas@glider.be
2023-03-06clk: renesas: r8a77995: Fix VIN parent clockGeert Uytterhoeven1-1/+1
According to the R-Car Series, 3rd Generation Hardware User’s Manual Rev. 2.30, the parent clock of the Video Input Module (VIN) on R-Car D3 is S3D1. Update the driver to match the documentation. This has no functional impact, as both S1D2 and S3D1 have the same clock rate, and are always-on clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/9b655843a260e06fa6f3349cdafac180e2bf38a5.1676368776.git.geert+renesas@glider.be
2023-03-06clk: renesas: r8a77980: Add VIN clocksNiklas Söderlund1-0/+16
Add the VIN module clocks, which are used by the VIN modules on the Renesas R-Car V3H (R8A77980) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211153026.3898491-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06clk: renesas: r8a779g0: Add VIN clocksNiklas Söderlund1-0/+16
Add the VIN module clocks, which are used by the VIN modules on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211143655.3809756-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06clk: renesas: r8a779g0: Add ISPCS clocksNiklas Söderlund1-0/+2
Add the ISPCS0 and ISPCS1 module clocks, which are used by the ISPCS modules on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211143655.3809756-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06clk: renesas: r8a779g0: Add CSI-2 clocksNiklas Söderlund1-0/+3
Add the CSI core clock and the CSI40 and CSI41 module clocks, which are used by the CSI-2 Interfaces on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211143655.3809756-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06clk: renesas: r8a779g0: Add thermal clockGeert Uytterhoeven1-0/+1
Add the module clock used by the Thermal Sensor/Chip Internal Voltage Monitor/Core Voltage Monitor (THS/CIVM/CVM) on the Renesas R-Car V4H (R8A779G0) SoC. Based on a large patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/59461effd0d9f7a39e0c91352c87f2b7071b1891.1675958536.git.geert+renesas@glider.be
2023-03-06clk: renesas: r8a779g0: Add Audio clocksKuninori Morimoto1-0/+2
Add module clocks for the Audio (SSI/SSIU) blocks on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/878rhganfo.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4HTakeshi Kihara1-4/+4
The SRCR, SRSTCLR, MSTPCR and MSTPSR registers for R-Car V4H (R8A779G0) each have registers up to offset 0x74. Update the corresponding arrays. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87a61wanfx.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-02-10clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*Wolfram Sang5-173/+13
R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support for this SoC. Public users only have ES2 onwards. In addition to the ES1 specific removals, a check for it was added preventing the machine to boot further. It may otherwise inherit wrong clock settings from ES2 which could damage the hardware. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230202092332.2504-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-26clk: renesas: r8a779g0: Add CAN-FD clocksGeert Uytterhoeven1-0/+2
Add the CANFD core clock and the CANFD0 module clock, which are used by the CAN-FD Interface on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a78f534bd80f170f3f1267f3270fdb3b7a73b5d4.1674498643.git.geert+renesas@glider.be
2023-01-26clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMACKuninori Morimoto1-2/+2
"sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87v8l3z3y8.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-26clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMACKuninori Morimoto1-2/+2
"sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87tu0nz3xr.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-24clk: renesas: r8a779g0: Add custom clock for PLL2Geert Uytterhoeven3-7/+164
Currently the PLLs are modeled as fixed factor clocks, based on initial settings. However, enabling CPU boost clock rates requires increasing the PLL clock rates. Add a custom clock driver to model the PLL clocks on R-Car Gen4, and use it for PLL2 on R-Car V4H. This allows the Z clock (Cortex-A76 core clock) to request PLL rate changes, and enable boost mode for the High Performance mode. For now this is limited to integer multiplication modes. Note that the definition for CPG_PLLxCR0_NI uses the value for R-Car V4H. On R-Car S4-8, the integer and fractional multiplication fields are one bit larger resp. smaller, but R-Car S4-8 does not support High Performance mode. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/76a5952900a6e15604c640bc8a27762e0e936677.1670492384.git.geert+renesas@glider.be
2023-01-23clk: renesas: cpg-mssr: Remove superfluous check in resume codeGeert Uytterhoeven1-3/+2
When the code flow arrives at printing the error message in cpg_mssr_resume_noirq(), we know for sure that we are not running on an RZ/A Soc, as the code checked for that before. Fixes: ace342097768e35f ("clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/144a3e66d748c0c17f3524ac8fa6ece5bf5b6f1e.1673425314.git.geert+renesas@glider.be
2023-01-23clk: renesas: r9a06g032: Handle h2mode setting based on USBF presenceHerve Codina1-0/+28
The CFG_USB[H2MODE] allows to switch the USB configuration. The configuration supported are: - One host and one device or - Two hosts Set CFG_USB[H2MODE] based on the USBF controller (USB device) availability. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230105152257.310642-3-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-12clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failedAlexey Khoroshilov1-1/+2
If cpg_mssr_common_init() fails after assigning priv to global variable cpg_mssr_priv, it deallocates priv, but cpg_mssr_priv keeps dangling pointer that potentially can be used later. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 1f7db7bbf031 ("clk: renesas: cpg-mssr: Add early clock support") Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1671806417-32623-1-git-send-email-khoroshilov@ispras.ru Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-12clk: renesas: r9a07g044: Add clock and reset entries for CRULad Prabhakar1-1/+25
Add CRU clock and reset entries to CPG driver. CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular sequence for the CRU block hence add these clocks to r9a07g044_no_pm_mod_clks[] array and pass it as part of CPG data for both RZ/G2L and RZ/V2L SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221221212703.348278-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-12-27clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entriesPhil Edworthy1-0/+20
Add SDHI/eMMC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221213230129.549968-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-12-27clk: renesas: r9a09g011: Add USB clock and reset entriesBiju Das1-0/+21
Add USB clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221212172804.1277751-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-06 23:29:57 +0300