Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2021-03-30 | clk: renesas: Zero init clk_init_data | Geert Uytterhoeven | 1 | -4/+4 |
2021-03-24 | clk: renesas: Couple of spelling fixes | Bhaskar Chowdhury | 1 | -2/+2 |
2020-12-08 | clk: renesas: r9a06g032: Drop __packed for portability | Geert Uytterhoeven | 1 | -1/+1 |
2020-04-14 | clk: renesas: r9a06g032: Fix some typo in comments | Christophe JAILLET | 1 | -3/+3 |
2019-08-23 | clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain | Geert Uytterhoeven | 1 | -1/+2 |
2019-06-04 | clk: renesas: r9a06g032: Add clock domain support | Gareth Williams | 1 | -69/+158 |
2019-05-15 | clk: Remove io.h from clk-provider.h | Stephen Boyd | 1 | -0/+1 |
2019-04-02 | clk: renesas: r9a06g032: Add missing PCI USB clock | Gareth Williams | 1 | -0/+1 |
2018-12-11 | clk: renesas: Remove usage of CLK_IS_BASIC | Stephen Boyd | 1 | -4/+4 |
2018-09-11 | clk: renesas: r9a06g032: Fix UART34567 clock rate | Phil Edworthy | 1 | -1/+2 |
2018-06-25 | clk: renesas: Renesas R9A06G032 clock driver | Michel Pollet | 1 | -0/+893 |