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2020-01-27clk: qcom: Fix -Wunused-const-variableNathan Huckleberry1-36/+0
[ Upstream commit da642427bd7710ec4f4140f693f59aa8521a358c ] Clang produces the following warning drivers/clk/qcom/gcc-msm8996.c:133:32: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map' [-Wunused-const-variable] static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = { ^drivers/clk/qcom/gcc-msm8996.c:141:27: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div' [-Wunused-const-variable] static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = { ^ drivers/clk/qcom/gcc-msm8996.c:187:32: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map' [-Wunused-const-variable] static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = { ^ drivers/clk/qcom/gcc-msm8996.c:197:27: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div' [-Wunused-const-variable] static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = { It looks like these were never used. Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Cc: clang-built-linux@googlegroups.com Link: https://github.com/ClangBuiltLinux/linux/issues/518 Suggested-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Nathan Huckleberry <nhuck@google.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-01-27clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998Marc Gonzalez1-1/+1
[ Upstream commit c0ee0e43c049a13d11e913edf875e4ee376dc84b ] See similar issue solved by commit 5f2420ed2189 ("clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998") Without this patch, PCIe PHY init fails: qcom-qmp-phy 1c06000.phy: pipe_clk enable failed err=-16 phy phy-1c06000.phy.0: phy init failed --> -16 Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org> Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-01-23clk: qcom: gcc-sdm845: Add missing flag to votable GDSCsGeorgi Djakov1-0/+7
commit 5e82548e26ef62e257dc2ff37c11acb5eb72728e upstream. On sdm845 devices, during boot we see the following warnings (unless we have added 'pd_ignore_unused' to the kernel command line): hlos1_vote_mmnoc_mmu_tbu_sf_gdsc status stuck at 'on' hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc status stuck at 'on' hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc status stuck at 'on' hlos1_vote_aggre_noc_mmu_tbu2_gdsc status stuck at 'on' hlos1_vote_aggre_noc_mmu_tbu1_gdsc status stuck at 'on' hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc status stuck at 'on' hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc status stuck at 'on' As the name of these GDSCs suggests, they are "votable" and in downstream DT, they all have the property "qcom,no-status-check-on-disable", which means that we should not poll the status bit when we disable them. Luckily the VOTABLE flag already exists and it does exactly what we need, so let's make use of it to make the warnings disappear. Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") Reported-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lkml.kernel.org/r/20191126153437.11808-1-georgi.djakov@linaro.org Tested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-04clk: qcom: Allow constant ratio freq tables for rcgJeffrey Hugo2-0/+5
[ Upstream commit efd164b5520afd6fb2883b68e0d408a7de29c491 ] Some RCGs (the gfx_3d_src_clk in msm8998 for example) are basically just some constant ratio from the input across the entire frequency range. It would be great if we could specify the frequency table as a single entry constant ratio instead of a long list, ie: { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }, { } So, lets support that. We need to fix a corner case in qcom_find_freq() where if the freq table is non-null, but has no frequencies, we end up returning an "entry" before the table array, which is bad. Then, we need ignore the freq from the table, and instead base everything on the requested freq. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191031185715.15504-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-13clk: qcom: gcc-msm8998: Disable halt check of UFS clocksBjorn Andersson1-3/+3
[ Upstream commit 2abf856202fd3e4883e4c518acaa9a023b0dbe54 ] Drop the halt check of the UFS symbol clocks, in accordance with other platforms. This makes clk_disable_unused() happy and makes it possible to turn the clocks on again without an error. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-13clk: qcom: Fix MSM8998 resetsJeffrey Hugo1-19/+19
[ Upstream commit 4f89f7b59a6ea17e81cff212c18a0b580ff5ff27 ] The offsets for the defined BCR reset registers does not match the hardware documentation. Update the values to match the hardware documentation. Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver) Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-10-07clk: qcom: gcc-sdm845: Use floor ops for sdcc clksStephen Boyd1-2/+2
[ Upstream commit 5e4b7e82d497580bc430576c4c9bce157dd72512 ] Some MMC cards fail to enumerate properly when inserted into an MMC slot on sdm845 devices. This is because the clk ops for qcom clks round the frequency up to the nearest rate instead of down to the nearest rate. For example, the MMC driver requests a frequency of 52MHz from clk_set_rate() but the qcom implementation for these clks rounds 52MHz up to the next supported frequency of 100MHz. The MMC driver could be modified to request clk rate ranges but for now we can fix this in the clk driver by changing the rounding policy for this clk to be round down instead of round up. Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") Reported-by: Douglas Anderson <dianders@chromium.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lkml.kernel.org/r/20190830195142.103564-1-swboyd@chromium.org Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-08clk: qcom: Add missing freq for usb30_master_clk on 8998Jeffrey Hugo1-0/+1
commit 0c8ff62504e3a667387e87889a259632c3199a86 upstream. The usb30_master_clk supports a 60Mhz frequency, but that is missing from the table of supported frequencies. Add it. Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver) Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-03-14clk: qcom: gcc: Use active only source for CPUSS clocksTaniya Das1-4/+10
[ Upstream commit 9ff1a3b4912528f853048ccd9757ba6a2cc75557 ] The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL clock and needs to vote on the active only source of XO, so as to keep the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has the same requirement. Signed-off-by: Taniya Das <tdas@codeaurora.org> Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2018-08-16Merge tag 'clk-for-linus' of ↵Linus Torvalds30-129/+1089
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The new and exciting feature this time around is in the clk core. We've added duty cycle support to the clk API so that clk signal duty cycle ratios can be adjusted while taking into account things like clk dividers and clk tree hierarchy. So far only one SoC has implemented support for this, but I expect there will be more to come in the future. Outside of the core, we have the usual pile of clk driver updates and additions. The Amlogic meson driver got the most lines in the diffstat this time around because it added support for a whole bunch of hardware and duty cycle configuration. After that the Rockchip PX30, Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the diff. We're left with the collection of non-critical fixes after that. Overall it looks pretty quiet this time. Core: - Clk duty cycle support - Proper CLK_SET_RATE_GATE support throughout the tree New Drivers: - Actions Semi Owl series S700 SoC clk driver - Qualcomm SDM845 display clock controller - i.MX6SX ocram_s clk support - Uniphier NAND, USB3 PHY, and SPI clk support - Qualcomm RPMh clk driver - i.MX7D mailbox clk support - Maxim 9485 Programmable Clock Generator - expose 32 kHz PLL on PXA SoCs - imx6sll GPIO clk gate support - Atmel at91 I2S audio clk support - SI544/SI514 clk on/off support - i.MX6UL GPIO clock gates in CCM CCGR - Renesas Crypto Engine clocks on R-Car H3 - Renesas clk support for the new RZ/N1D SoC - Allwinner A64 display engine clock support - support for Rockchip's PX30 SoC - Amlogic Meson axg PCIe and audio clocks - Amlogic Meson GEN CLK on gxbb, gxl and axg Updates: - remove an unused variable from Exynos4412 ISP driver - fix a thinko bug in SCMI clk division logic - add missing of_node_put()s in some i.MX clk drivers - Tegra SDMMC clk jitter improvements with high speed signaling modes - SPDX tagging for qcom and cs2000-cp drivers - stop leaking con ids in __clk_put() - fix a corner case in fixed factor clk probing where node is in DT but parent clk is registered much later - Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return value - i.MX clk init arrays removed in place of CLK_IS_CRITICAL - convert to CLK_IS_CRITICAL for i.MX51/53 driver - fix Tegra BPMP driver oops when xlating a NULL clk - proper default configuration for vic03 and vde clks on Tegra124 - mark Tegra memory controller clks as critical - fix array bounds clamp in Tegra's emc determine_rate() op - Ingenic i2s bit update and allow UDC clk to gate - fix name of aspeed SDC clk define to have only one 'CLK' - fix i.MX6QDL video clk parent - critical clk markings for qcom SDM845 - fix Stratix10 mpu_free_clk and sdmmc_free_clk parents - mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it supplying the pwm used to drive the logic supply of the rk3399 core" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (85 commits) clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 clk: cs2000-cp: convert to SPDX identifiers clk: scmi: Fix the rounding of clock rate clk: qcom: Add display clock controller driver for SDM845 clk: mvebu: armada-37xx-periph: Remove unused var num_parents clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable clk: actions: Add S700 SoC clock support dt-bindings: clock: Add S700 support for Actions Semi Soc's clk: actions: Add missing REGMAP_MMIO dependency clk: uniphier: add clock frequency support for SPI clk: uniphier: add more USB3 PHY clocks clk: uniphier: add NAND 200MHz clock clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks clk: tegra: Add sdmmc mux divider clock clk: tegra: Refactor fractional divider calculation clk: tegra: Fix includes required by fence_udelay() clk: imx6sll: fix missing of_node_put() clk: imx6ul: fix missing of_node_put() clk: imx: add ocram_s clock for i.mx6sx clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent ...
2018-08-15Merge branches 'clk-actions-s700', 'clk-exynos-unused', ↵Stephen Boyd17-26/+698
'clk-qcom-dispcc-845', 'clk-scmi-round' and 'clk-cs2000-spdx' into clk-next * clk-actions-s700: : - Actions Semi Owl series S700 SoC clk driver clk: actions: Add S700 SoC clock support dt-bindings: clock: Add S700 support for Actions Semi Soc's clk: actions: Add missing REGMAP_MMIO dependency * clk-exynos-unused: : - Remove an unused variable from Exynos4412 ISP driver clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable * clk-qcom-dispcc-845: : - Qualcomm SDM845 display clock controller clk: qcom: Add display clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Display clock bindings clk: qcom: Move frequency table macro to common file * clk-scmi-round: : - Fix a thinko bug in SCMI clk division logic clk: scmi: Fix the rounding of clock rate * clk-cs2000-spdx: clk: cs2000-cp: convert to SPDX identifiers
2018-08-15Merge branches 'clk-qcom-rpmh', 'clk-qcom-spdx', 'clk-con-id-leak', ↵Stephen Boyd11-84/+352
'clk-fixed-factor-populated' and 'clk-mvebu-periph-parent' into clk-next * clk-qcom-rpmh: : - Qualcomm RPMh clk driver clk: qcom: clk-rpmh: Add QCOM RPMh clock driver * clk-qcom-spdx: : - SPDX tagging for qcom clk: qcom: Update SPDX headers for common files * clk-con-id-leak: : - Stop leaking con ids in __clk_put() clk: core: Potentially free connection id * clk-fixed-factor-populated: : - Fix a corner case in fixed factor clk probing where node is in DT but : parent clk is registered much later clk: clk-fixed-factor: Clear OF_POPULATED flag in case of failure * clk-mvebu-periph-parent: : - Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return value clk: mvebu: armada-37xx-periph: Remove unused var num_parents clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent
2018-08-15Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', ↵Stephen Boyd1-4/+39
'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next * clk-imx6-video-parent: : - Fix i.MX6QDL video clk parent clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL * clk-qcom-sdm845-criticals: : - critical clk markings for qcom SDM845 clk: qcom: Enable clocks which needs to be always on for SDM845 * clk-renesas: clk: renesas: Renesas R9A06G032 clock driver dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation dt-bindings: clock: Add the r9a06g032-sysctrl.h file clk: renesas: r8a7795: Add CCREE clock clk: renesas: r8a7795: Add CR clock * clk-stratix10-fixes: : - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents clk: socfpga: stratix10: fix the sdmmc_free_clk mux clk: socfpga: stratix10: fix the parents of mpu_free_clk * clk-atmel-i2s: : - Atmel at91 I2S audio clk support clk: at91: add I2S clock mux driver dt-bindings: clk: at91: add an I2S mux clock
2018-08-01clk: qcom: Add display clock controller driver for SDM845Taniya Das3-0/+696
Add support for the display clock controller found on SDM845 based devices. This would allow display drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Remove CLK_GET_RATE_NOCACHE everywhere] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-25clk: qcom: Update SPDX headers for common filesTaniya Das8-84/+13
SPDX headers updated for common/branch/pll/regmap files. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-16clk: qcom: clk-rpmh: Add QCOM RPMh clock driverTaniya Das3-0/+339
Add the RPMh clock driver to control the RPMh managed clock resources on some of the Qualcomm Technologies, Inc. SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Clean up whitespace, indentation, remove cmd_db_ready check] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-07clk: qcom: Move frequency table macro to common fileTaniya Das14-26/+2
Frequency table macro is used by multiple clock drivers, move frequency table macro to common header file. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk/mmcc-msm8996: Make mmagic_bimc_gdsc ALWAYS_ONVivek Gautam1-0/+1
Patch (7705bb7176b9 clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled") makes all mmgaic gdscs ALWAYS_ON. The mmagic_bimc_gdsc is also needed to be turned on to get display working on 8x96. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 7705bb7176b9 ("clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: qcom: gcc-msm8996: Disable halt check on UFS tx clockVinod Koul1-0/+1
Commit 12d807cd34b8 ("clk: qcom: gcc-msm8996: Disable halt check on UFS clocks") marked BRANCH_HALT_SKIP for ufs rx clocks, but missed ufs tx clocks. The result of that is kernel warnings at reboot: [ 105.624283] gcc_ufs_tx_symbol_0_clk status stuck at 'on' [ 105.624311] WARNING: CPU: 1 PID: 1 at drivers/clk/qcom/clk-branch.c:100 clk_branch_toggle+0x190/0x1b0 [ 105.633235] Modules linked in: [ 105.645118] CPU: 1 PID: 1 Comm: systemd-shutdow Tainted: G W 4.18.0-rc2-00002-g2bfbe52a53a3 #11 [ 105.647988] Hardware name: Qualcomm Technologies, Inc. DB820c (DT) [ 105.657966] pstate: 60000085 (nZCv daIf -PAN -UAO) [ 105.664127] pc : clk_branch_toggle+0x190/0x1b0 [ 105.668900] lr : clk_branch_toggle+0x190/0x1b0 [ 105.673324] sp : ffff00000805bb40 [ 105.677751] x29: ffff00000805bb40 x28: 0000000000000000 [ 105.681140] x27: ffff8000d947cc60 x26: 0000000000000001 [ 105.686520] x25: ffff000008f71900 x24: 0000000000000000 [ 105.691816] x23: ffff00000925e338 x22: ffff00000855f8e0 [ 105.697114] x21: 0000000000000000 x20: 0000000000000000 [ 105.702407] x19: ffff0000091c9000 x18: ffffffffffffffff [ 105.707702] x17: 0000ffffac148c58 x16: ffff000008b82928 [ 105.712998] x15: ffff0000091c96c8 x14: ffff0000893817c7 [ 105.718293] x13: ffff0000093817d5 x12: ffff0000091c9940 [ 105.723587] x11: ffff0000085e3e70 x10: ffff00000805b780 [ 105.728884] x9 : ffff00000805bb40 x8 : 7320737574617473 [ 105.734179] x7 : 206b6c635f305f6c x6 : 00000000000001e5 [ 105.739472] x5 : 0000000000000000 x4 : 0000000000000000 [ 105.744769] x3 : ffffffffffffffff x2 : ffff0000091e2658 [ 105.750063] x1 : a7c4712dd5e09c00 x0 : 0000000000000000 [ 105.755360] Call trace: [ 105.760652] clk_branch_toggle+0x190/0x1b0 [ 105.762824] clk_branch2_disable+0x18/0x20 [ 105.766994] clk_core_disable+0x58/0xa8 [ 105.771069] clk_core_disable_lock+0x20/0x38 [ 105.774803] clk_disable+0x1c/0x28 [ 105.779320] __ufshcd_setup_clocks+0x298/0x308 [ 105.782529] ufshcd_suspend+0x160/0x308 [ 105.786953] ufshcd_shutdown+0x38/0xa0 [ 105.790690] ufshcd_pltfrm_shutdown+0x10/0x18 [ 105.794512] platform_drv_shutdown+0x20/0x30 [ 105.798935] device_shutdown+0x110/0x1e8 [ 105.803278] kernel_restart_prepare+0x34/0x40 [ 105.807181] kernel_restart+0x14/0x78 [ 105.811434] sys_reboot+0x200/0x248 [ 105.815081] el0_svc_naked+0x30/0x34 [ 105.818378] ---[ end trace 8d2322276b27879c ]--- Mark gcc_ufs_tx_symbol_0_clk as BRANCH_HALT_SKIP as well. Fixes: 12d807cd34b8 ("clk: qcom: gcc-msm8996: Disable halt check on UFS clocks") Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-03clk: qcom: Enable clocks which needs to be always on for SDM845Amit Nischal1-4/+39
There are certain clocks which needs to be always enabled for system operation. Add support for the same by adding 'CLK_IS_CRITICAL' flag for such clocks. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-19clk: qcom: drop CLK_SET_RATE_GATE from sdc clocksJerome Brunet4-15/+0
the mmci driver (drivers/mmc/host/mmci.c) does the following sequence: * clk_prepare_enable() * clk_set_rate() on SDCx_clk which is a children of SDCx_src. SDCx_src has CLK_SET_RATE_GATE so this sequence should not be allowed but this was not enforced. IOW, the flag is ignored. Dropping the flag won't change anything to the current behaviour of the platform. CLK_SET_RATE_GATE is being fixed and enforced now. If the flag was kept, the mmci driver would receive -EBUSY when calling clk_set_rate() Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180619134051.16726-2-jbrunet@baylibre.com
2018-06-09Merge tag 'clk-for-linus' of ↵Linus Torvalds16-89/+7281
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time we have a good set of changes to the core framework that do some general cleanups, but nothing too major. The majority of the diff goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is introduced for Actions Semi so it takes up some lines to add all the different types, and the Qualcomm diff is there because we add support for two SoCs and it's quite a bit of data. Otherwise the big driver updates are on TI Davinci and Amlogic platforms. And then the long tail of driver updates for various fixes and stuff follows after that. Core: - debugfs cleanups removing error checking and an unused provider API - Removal of a clk init typedef that isn't used - Usage of match_string() to simplify parent string name matching - OF clk helpers moved to their own file (linux/of_clk.h) - Make clk warnings more readable across kernel versions New Drivers: - Qualcomm SDM845 GCC and Video clk controllers - Qualcomm MSM8998 GCC - Actions Semi S900 SoC support - Nuvoton npcm750 microcontroller clks - Amlogic axg AO clock controller Removed Drivers: - Deprecated Rockchip clk-gate driver Updates: - debugfs functions stopped checking return values - Support for the MSIOF module clocks on Rensas R-Car M3-N - Support for the new Rensas RZ/G1C and R-Car E3 SoCs - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs - Berlin and Amlogic SPDX tagging - Usage of of_clk_get_parent_count() in more places - Proper implementation of the CDEV1/2 clocks on Tegra20 - Allwinner H6 PRCM clock support and R40 EMAC support - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet - Round closest support for meson's mpll driver - Support for meson8b nand clocks and gxbb video decoder clocks - Mediatek mali clks - STM32MP1 fixes - Uniphier LD11/LD20 stream demux system clock" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) clk: qcom: Export clk_fabia_pll_configure() clk: bcm: Update and add Stingray clock entries dt-bindings: clk: Update Stingray binding doc clk-si544: Properly round requested frequency to nearest match clk: ingenic: jz4770: Add 150us delay after enabling VPU clock clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle clk: ingenic: jz4770: Change OTG from custom to standard gated clock clk: ingenic: Support specifying "wait for clock stable" delay clk: ingenic: Add support for clocks whose gate bit is inverted clk: use match_string() helper clk: bcm2835: use match_string() helper clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions clk: imx6: add EPIT clock support clk: mvebu: use correct bit for 98DX3236 NAND ...
2018-06-06treewide: Use struct_size() for devm_kmalloc() and friendsKees Cook1-2/+1
Replaces open-coded struct size calculations with struct_size() for devm_*, f2fs_*, and sock_* allocations. Automatically generated (and manually adjusted) from the following Coccinelle script: // Direct reference to struct field. @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP) + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP) // mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL); @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP) + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP) // Same pattern, but can't trivially locate the trailing element name, // or variable name. @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; expression SOMETHING, COUNT, ELEMENT; @@ - alloc(HANDLE, sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP) + alloc(HANDLE, CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP) Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-04Merge branch 'clk-qcom-8996-halt' into clk-nextStephen Boyd1-0/+6
* clk-qcom-8996-halt: clk: qcom: gcc-msm8996: Disable halt check on UFS clocks clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk
2018-06-04Merge branch 'clk-qcom-sdm845' into clk-nextStephen Boyd12-62/+4395
* clk-qcom-sdm845: clk: qcom: Export clk_fabia_pll_configure() clk: qcom: Add video clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Video clock bindings clk: qcom: Add Global Clock controller (GCC) driver for SDM845 clk: qcom: Add DT bindings for SDM845 gcc clock controller clk: qcom: Configure the RCGs to a safe source as needed clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks clk: qcom: Simplify gdsc status checking logic clk: qcom: gdsc: Add support to poll CFG register to check GDSC state clk: qcom: gdsc: Add support to poll for higher timeout value clk: qcom: gdsc: Add support to reset AON and block reset logic clk: qcom: Add support for controlling Fabia PLL clk: qcom: Clear hardware clock control bit of RCG Also fixup the Kconfig mess where SDM845 GCC has msm8998 in the description and also the video Kconfig says things slightly differently from the GCC one so just make it the same.
2018-06-04Merge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' ↵Stephen Boyd5-28/+37
and 'clk-qcom-mmagic' into clk-next * clk-allwinner: clk: sunxi-ng: r40: export a regmap to access the GMAC register clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: add support for H6 PRCM CCU * clk-rockchip: clk: rockchip: remove deprecated gate-clk code and dt-binding clk: rockchip: use match_string() helper * clk-tegra: clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 clk: tegra20: Correct parents of CDEV1/2 clocks clk: tegra20: Add DEV1/DEV2 OSC dividers * clk-berlin: clk: berlin: switch to SPDX license identifier * clk-qcom-mmagic: clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled clk: qcom: Register the gdscs before the clocks clk: qcom: gdsc: Add support for ALWAYS_ON gdscs
2018-06-04Merge branches 'clk-qcom-rpmh', 'clk-npcm7xx', 'clk-of-parent-count' and ↵Stephen Boyd1-0/+1
'clk-qcom-rcg-fix' into clk-next * clk-qcom-rpmh: dt-bindings: clock: Introduce QCOM RPMh clock bindings * clk-npcm7xx: clk: npcm7xx: fix return value check in npcm7xx_clk_init() clk: npcm7xx: add clock controller dt-binding: clk: npcm750: Add binding for Nuvoton NPCM7XX Clock * clk-of-parent-count: pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding soc/tegra: pmc: Use of_clk_get_parent_count() instead of open coding soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding ARM: timer-sp: Use of_clk_get_parent_count() instead of open coding clk: Extract OF clock helpers in <linux/of_clk.h> * clk-qcom-rcg-fix: clk: qcom: Base rcg parent rate off plan frequency
2018-06-02clk: qcom: Export clk_fabia_pll_configure()Stephen Boyd1-0/+1
This is used by the video clk driver on sdm845 and that's a module. Export it to prevent module build failures. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01clk: qcom: gcc-msm8996: Disable halt check on UFS clocksBjorn Andersson1-0/+2
The halt check of the UFS symbol clocks always fails, as such probing UFS after clk_disable_unused always fails. This makes it impossible to boot a system with the UFS phy or UFS HCD drivers compiled as modules. Follow SDM845 and disable the halt check on these clocks. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01clk: qcom: Add video clock controller driver for SDM845Amit Nischal3-0/+370
Add support for the video clock controller found on SDM845 based devices. This would allow video drivers to probe and control their clocks. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clkManu Gautam1-0/+4
The USB and PCIE pipe clocks are sourced from external clocks inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG clocks is dependent on PHY initialization sequence hence update halt_check to BRANCH_HALT_SKIP for these clocks so that clock status bit is not polled when enabling or disabling the clocks. It allows to simplify PHY client driver code which is both user and source of the pipe_clk and avoid error logging related status check on clk_disable/enable. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabledRajendra Nayak2-12/+12
There's no bus infrastructure today to handle all the mmagic bus clocks and GDSCs needed by all the multimedia blocks in msm8996, like mdss, video, camera and gpu. Mark all these clocks with a CLK_IS_CRITICAL and GDSCs with a ALWAYS_ON flag for now so they are left always enabled. This patch should be reverted at some point when we do have a bus driver to manage these clocks and GDSCs. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01clk: qcom: Register the gdscs before the clocksRajendra Nayak1-16/+16
We have atleast some instances of ALWAYS_ON gdscs, which need to be turned ON *before* some clocks within the gdsc domain marked with a CLK_IS_CRITICAL can be turned ON. To facilitate this sequence, register the GDCSs (and hence handle the ALWAYS_ON gdscs) before we register clocks (and handle the clocks marked as CLK_IS_CRITICAL) Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01clk: qcom: gdsc: Add support for ALWAYS_ON gdscsRajendra Nayak2-0/+9
Some GDSCs might have software control to turn them off, but we might want to keep them enabled always, in some cases because of lack of support in kernel to handle a graceful turning off/on of such GDSCs. Most common instances would be the GDCSs which power up the noc/bus fabrics, which need bus drivers to handle them and atleast support for which is missing on all qcom SoCs. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-10clk: qcom: Base rcg parent rate off plan frequencyEvan Green1-0/+1
_freq_tbl_determine_rate uses the pre_div found in the clock plan multiplied by the requested rate from the caller to determine the best parent rate to set. If the requested rate is not exactly equal to the rate that was found in the clock plan, then using the requested rate in parent rate calculations is incorrect. For instance, if 150MHz was requested, but 200MHz was the match found, and that plan had a pre_div of 3, then the parent should be set to 600MHz, not 450MHz. Signed-off-by: Evan Green <evgreen@chromium.org> Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-08clk: qcom: Add Global Clock controller (GCC) driver for SDM845Taniya Das3-0/+3475
Add support for the global clock controller found on SDM845 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-08clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocksAmit Nischal2-2/+6
There could be few clocks where the clock status bit is not required to be polled as the clock on/off would be controlled by enabling/disabling external source. Add support for the same by introducing new flag named as 'BRANCH_HALT_SKIP'. Signed-off-by: Amit Nischal <anischal@codeaurora.org> [sboyd@kernel.org: Rename flag to BRANCH_HALT_SKIP] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-08clk: qcom: Simplify gdsc status checking logicStephen Boyd1-19/+37
The code is complicated because we want to check if the GDSC is enabled or disabled based on different bits in different registers while the GDSC hardware is slightly different across chips. Furthermore, we poll the status of the enable or disable state by checking if the gdsc is enabled or not, and then comparing that to if the gdsc is being enabled or disabled. Let's push all that into one function, so we can ask if the status matches what we want, either on or off. Then the call site can just ask that question, and the logic to check that state can simply return yes or no, and not 1 or 0 or 0 or 1 depending on if we're enabling or disabling respectively. Tested-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-08clk: qcom: Configure the RCGs to a safe source as neededAmit Nischal2-24/+155
For some root clock generators, there could be child branches which are controlled by an entity other than application processor subsystem. For such RCGs, as per application processor subsystem clock driver, all of its downstream clocks are disabled and RCG is in disabled state but in reality downstream clocks can be left enabled before. So in this scenario, when RCG is disabled as per clock driver's point of view and when rate scaling request comes before downstream clock enable request, then RCG fails to update its configuration because in reality RCG is on and it expects its new source to already be in enable state but in reality new source is off. In order to avoid having the RCG to go into an invalid state, add support to update the CFG, M, N and D registers during set_rate() without configuration update and defer the actual RCG configuration update to be done during clk_enable() as at this point of time, both its new parent and safe source will be already enabled and RCG can safely switch to new parent. During clk_disable() request, configure it to safe source as both its parents, safe source and current parent will be enabled and RCG can safely execute a switch. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-02clk: qcom: gdsc: Add support to poll CFG register to check GDSC stateAmit Nischal2-16/+27
The default behavior of the GDSC enable/disable sequence is to poll the status bits of either the actual GDSCR or the corresponding HW_CTRL registers. On targets which have support for a CFG_GDSCR register, the status bits might not show the correct state of the GDSC, especially in the disable sequence, where the status bit will be cleared even before the core is completely power collapsed. On targets with this issue, poll the power on/off bits in the CFG_GDSCR register instead to correctly determine the GDSC state. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-17clk: qcom: Add MSM8998 Global Clock Control (GCC) driverJoonwoo Park3-0/+2843
Add support for the global clock controller found on MSM8998 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Imran Khan <kimran@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [bjorn: Specify regs for alpha_plls, fix white spaces and add binding] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-17clk: qcom: gdsc: Add support to poll for higher timeout valueAmit Nischal1-1/+1
For some gdscs, it might take longer time up to 500us for updating their status. Update the timeout value for all GDSC polling status. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-17clk: qcom: gdsc: Add support to reset AON and block reset logicAmit Nischal2-3/+23
For some of the gdsc power domains, there could be need to reset the AON logic or assert/deassert the block control reset before removing the clamp_io. Add support for the same by introducing new flags SW_RESET and AON_RESET. Both SW reset and AON reset requires to be asserted for at least 1us before being de-asserted. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-14Merge tag 'clk-for-linus' of ↵Linus Torvalds4-27/+89
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The large diff this time around is from the addition of a new clk driver for the TI Davinci family of SoCs. So far those clks have been supported with a custom implementation of the clk API in the arch port instead of in the CCF. With this driver merged we're one step closer to having a single clk API implementation. The other large diff is from the Amlogic clk driver that underwent some major surgery to use regmap. Beyond that, the biggest hitter is Samsung which needed some reworks to properly handle clk provider power domains and a bunch of PLL rate updates. The core framework was fairly quiet this round, just getting some cleanups and small fixes for some of the more esoteric features. And the usual set of driver non-critical fixes, cleanups, and minor additions are here as well. Core: - Rejig clk_ops::init() to be a little earlier for phase/accuracy ops - debugfs ops macroized to shave some lines of boilerplate code - Always calculate the phase instead of caching it in clk_get_phase() - More __must_check on bulk clk APIs New Drivers: - TI's Davinci family of SoCs - Intel's Stratix10 SoC - stm32mp157 SoC - Allwinner H6 CCU - Silicon Labs SI544 clock generator chip - Renesas R-Car M3-N and V3H SoCs - i.MX6SLL SoCs Removed Drivers: - ST-Ericsson AB8540/9540 Updates: - Mediatek MT2701 and MT7622 audsys support and MT2712 updates - STM32F469 DSI and STM32F769 sdmmc2 support - GPIO clks can sleep now - Spreadtrum SC9860 RTC clks - Nvidia Tegra MBIST workarounds and various minor fixes - Rockchip phase handling fixes and a memory leak plugged - Renesas drivers switch to readl/writel from clk_readl/clk_writel - Renesas gained CPU (Z/Z2) and watchdog support - Rockchip rk3328 display clks and rk3399 1.6GHz PLL support - Qualcomm PM8921 PMIC XO buffers - Amlogic migrates to regmap APIs - TI Keystone clk latching support - Allwinner H3 and H5 video clk fixes - Broadcom BCM2835 PLLs needed another bit to enable - i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix - i.MX6UL/ULL epdc_podf support - Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (233 commits) clk: davinci: add a reset lookup table for psc0 clk: imx: add clock driver for imx6sll dt-bindings: imx: update clock doc for imx6sll clk: imx: add new gate/gate2 wrapper funtion clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux clk: cs2000: set pm_ops in hibernate-compatible way clk: bcm2835: De-assert/assert PLL reset signal when appropriate clk: imx7d: Move clks_init_on before any clock operations clk: imx7d: Correct ahb clk parent select clk: imx7d: Correct dram pll type clk: imx7d: Add USB clock information clk: socfpga: stratix10: add clock driver for Stratix10 platform dt-bindings: documentation: add clock bindings information for Stratix10 clk: ti: fix flag space conflict with clkctrl clocks clk: uniphier: add additional ethernet clock lines for Pro4 clk: uniphier: add SATA clock control support clk: uniphier: add PCIe clock control support clk: Add driver for the si544 clock generator chip clk: davinci: Remove redundant dev_err calls clk: uniphier: add ethernet clock control support for PXs3 ...
2018-04-06Merge branches 'clk-mvebu', 'clk-phase', 'clk-nxp', 'clk-mtk2712' and ↵Stephen Boyd1-1/+78
'clk-qcom-rpmcc' into clk-next * clk-mvebu: clk: mvebu: armada-38x: add support for missing clocks clk: mvebu: cp110: Fix clock tree representation * clk-phase: clk: Don't show the incorrect clock phase clk: update cached phase to respect the fact when setting phase * clk-nxp: clk: lpc32xx: Set name of regmap_config * clk-mtk2712: clk: mediatek: update clock driver of MT2712 dt-bindings: clock: add clocks for MT2712 * clk-qcom-rpmcc: clk: qcom: rpmcc: Add support to XO buffered clocks
2018-04-06Merge branches 'clk-versatile', 'clk-doc', 'clk-must-check', 'clk-qcom' and ↵Stephen Boyd2-12/+5
'clk-debugfs' into clk-next * clk-versatile: clk: versatile: Remove WARNs in ->round_rate() clk: versatile: add min/max rate boundaries for vexpress osc clock * clk-doc: Documentation: clk: enable lock is not held for clk_is_enabled API * clk-must-check: clk: add more __must_check for bulk APIs * clk-qcom: clk: qcom: smd-rpm: Migrate to devm_of_clk_add_hw_provider() clk: qcom: gcc-msm8996: Mark aggre0 noc clks as critical * clk-debugfs: clk: Re-use DEFINE_SHOW_ATTRIBUTE() macro
2018-03-20clk: qcom: Add support for controlling Fabia PLLAmit Nischal2-8/+311
Fabia PLL is a Digital Frequency Locked Loop (DFLL) clock generator which has a wide range of frequency output. It supports dynamic updating of the output frequency ("frequency slewing") without need to turn off the PLL before configuration. Add support for initial configuration and programming sequence to control fabia PLLs. Signed-off-by: Amit Nischal <anischal@codeaurora.org> [sboyd: Shorten code a little] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: qcom: Clear hardware clock control bit of RCGAmit Nischal1-2/+3
For upcoming targets like sdm845, POR value of the hardware clock control bit is set for most of root clocks which needs to be cleared for software to be able to control. For older targets like MSM8996, this bit is reserved bit and having POR value as 0 so this patch will work for the older targets too. So update the configuration mask to take care of the same to clear hardware clock control bit. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: qcom: rpmcc: Add support to XO buffered clocksSrinivas Kandagatla1-1/+78
XO is onchip buffer clock to generate 19.2MHz. This patch adds support to 5 XO buffer clocks found on PMIC8921, these buffer clocks can be controlled from external pin or in manual mode. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-17clk: qcom: smd-rpm: Migrate to devm_of_clk_add_hw_provider()Stephen Boyd1-8/+1
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-04 18:34:32 +0300