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2024-02-07clk: qcom: gcc-sc8280xp: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8280 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-6-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sc8180x: Set delay for Venus CLK resetsKonrad Dybcio1-3/+3
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-5-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sa8775p: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8775 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-4-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: reset: Ensure write completion on reset de/assertionKonrad Dybcio1-1/+6
Trying to toggle the resets in a rapid fashion can lead to the changes not actually arriving at the clock controller block when we expect them to. This was observed at least on SM8250. Read back the value after regmap_update_bits to ensure write completion. Fixes: b36ba30c8ac6 ("clk: qcom: Add reset controller support") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-3-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: reset: Commonize the de/assert functionsKonrad Dybcio1-13/+9
They do the same thing, except the last argument of the last function call differs. Commonize them. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-2-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: reset: Increase max reset delayKonrad Dybcio1-1/+1
u8 limits us to 255 microseconds of delay. Promote the delay variable to u16 to hold bigger values. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-1-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add camcc clock driver for x1e80100Rajendra Nayak3-0/+2495
Add the camcc clock driver for x1e80100 Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-10-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add TCSR clock driver for x1e80100Abel Vesa3-0/+294
The TCSR clock controller found on X1E80100 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-9-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add GPU clock driver for x1e80100Rajendra Nayak3-0/+666
Add Graphics Clock Controller (GPUCC) support for X1E80100 platform. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-8-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add dispcc clock driver for x1e80100Rajendra Nayak3-0/+1729
Add the dispcc clock driver for x1e80100. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-7-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: clk-alpha-pll: Add support for zonda ole pll configureRajendra Nayak2-0/+20
Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-6-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30clk: qcom: gpucc-sc8280xp: Add external supply for GX gdscBjorn Andersson1-0/+1
On SA8295P and SA8540P the GFX rail is powered by a dedicated external regulator, instead of the rpmh-controlled "gfx.lvl". Define the "vdd-gfx" as the supply regulator for the GDSC, to cause the gdsc logic to look for, and control, this external power supply. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-3-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30clk: qcom: gdsc: Enable supply reglator in GPU GX handlerBjorn Andersson1-2/+10
The GX GDSC is modelled to aid the GMU in powering down the GPU in the event that the GPU crashes, so that it can be restarted again. But in the event that the power-domain is supplied through a dedicated regulator (in contrast to being a subdomin of another power-domain), something needs to turn that regulator on, both to make sure things are powered and to match the operation in gdsc_disable(). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-2-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28clk: qcom: gcc-sm8150: Add gcc video resets for sm8150Satya Priya Kakitapalli1-0/+3
Add gcc video axic, axi0 and axi1 resets for the global clock controller on sm8150. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240111-sm8150-dfs-support-v2-3-6edb44c83d3b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150Satya Priya Kakitapalli1-140/+209
QUPv3 clocks support DFS and thus register the RCGs which require support for the same. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240111-sm8150-dfs-support-v2-1-6edb44c83d3b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-23clk: qcom: gcc-sdm845: Add soft dependency on rpmhpdAmit Pundir1-0/+1
With the addition of RPMh power domain to the GCC node in device tree, we noticed a significant delay in getting the UFS driver probed on AOSP which futher led to mount failures because Android do not support rootwait. So adding a soft dependency on RPMh power domain which informs modprobe to load rpmhpd module before gcc-sdm845. Cc: stable@vger.kernel.org # v5.4+ Fixes: 4b6ea15c0a11 ("arm64: dts: qcom: sdm845: Add missing RPMh power domain to GCC") Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240123062814.2555649-1-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-23clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi operationMantas Pucka1-0/+17
Without it system hangs upon wifi firmware load. It should be enabled by remoteproc/wifi driver. Bindings already exist for it, so add it based on vendor code. Signed-off-by: Mantas Pucka <mantas@8devices.com> Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-19clk: qcom: gcc-x1e80100: Replace of_device.h with explicit includesStephen Rothwell1-1/+2
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. of_device.h isn't needed, but mod_devicetable.h and platform_device.h were implicitly included. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20231211160510.0aef871b@canb.auug.org.au [robh: Redo commit msg] Signed-off-by: Rob Herring <robh@kernel.org>
2024-01-13Merge tag 'clk-for-linus' of ↵Linus Torvalds19-63/+19232
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Only a couple new SoCs have support added this time, primarily for Qualcomm SM8650 based on the diffstat. Otherwise this is a collection of non-critical fixes and cleanups to various clk drivers and their DT bindings. Nothing is changed in the core clk framework this time, although there's a patch to fix a basic clk type initialization function. In general, this pile looks to be on the smaller side. New Drivers: - Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Mediatek MT7988 SoC clocks Updates: - Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP - Support for stm32mp25 clks - Add glitch free PLL setting support to si5351 clk driver - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 - Document bindings for i.MX93 ANATOP clock driver - Free clk_node in i.MX SCU driver for resource with different owner - Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15 - Fix the name of the fvco in i.MX pll14xx by renaming it to fout - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs - Reuse reset functionality in the Renesas RZ/G2L clock driver - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 - Cleanup variable init in Allwinner nkm module - Convert various DT bindings to YAML - A few kernel-doc fixes for Samsung SoC clock controllers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings ...
2023-12-19clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL configKonrad Dybcio1-0/+8
These values were missing. Add them. Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231219-topic-8650_clks-v1-2-5672bfa0eb05@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL configKonrad Dybcio1-0/+2
These values were missing. Add them. Fixes: 8676fd4f3874 ("clk: qcom: add the SM8650 GPU Clock Controller driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231219-topic-8650_clks-v1-1-5672bfa0eb05@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: dispcc-sm8550: Use the correct PLL configuration functionKonrad Dybcio1-2/+2
To ensure that all fields (particularly CAL_L and CAL_L_RINGOSC) are filled properly, use the correct prepare function for OLE PLLs. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-9-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: dispcc-sm8550: Update disp PLL settingsKonrad Dybcio1-0/+8
The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-8-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gpucc-sm8550: Update GPU PLL settingsKonrad Dybcio1-3/+3
The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: bfae40744b33 ("clk: qcom: gpucc-sm8550: Add support for graphics clock controller") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-7-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: Mark RCGs shared where applicableKonrad Dybcio1-43/+43
The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-6-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCsKonrad Dybcio1-0/+8
The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Following other recent Qualcomm platforms, describe this register and the corresponding mask for the PCIe (and _phy) GDSCs. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-5-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votableKonrad Dybcio1-4/+4
The PCIe GDSCs on most Qualcomm platforms expect the OS to always consider collapse requests as successful. This also concerns SM8550. Add the VOTABLE flag to the GDSCs in question to comply with these expectations. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flagKonrad Dybcio1-8/+8
All of the 8550's GCC GDSCs can and should use the retain registers so as not to lose their state when entering lower power modes. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-3-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16clk: qcom: camcc-sc8280xp: Prevent error pointer dereferenceDan Carpenter1-2/+3
If "regmap" is an error pointer then calling regmap_update_bits() will crash. We only need to call regmap_update_bits() if we had written to it earlier. Fixes: ff93872a9c61 ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/210d48ce-6ebc-4a6b-b30f-866d10d41a16@moroto.mountain Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16clk: qcom: videocc-sm8150: Add runtime PM supportSatya Priya Kakitapalli1-2/+18
Add runtime PM support to ensure the supply rails are enabled when necessary. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-4-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16clk: qcom: videocc-sm8150: Add missing PLL config propertySatya Priya Kakitapalli1-0/+1
When the driver was ported upstream, PLL test_ctl_hi1 register value was omitted. Add it to ensure the PLLs are fully configured. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-3-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16clk: qcom: videocc-sm8150: Update the videocc resetsSatya Priya Kakitapalli1-0/+4
Add all the available resets for the video clock controller on sm8150. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-2-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08clk: qcom: rpmh: Add support for X1E80100 rpmh clocksRajendra Nayak1-0/+24
Adds the RPMH clocks present in X1E80100 SoC Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-5-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08clk: qcom: Add Global Clock controller (GCC) driver for X1E80100Rajendra Nayak3-0/+6818
Add support for the global clock controller found on X1E80100 based devices. Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-3-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000Imran Shaik3-0/+2466
Add ECPRI Clock Controller (ECPRICC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-4-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: branch: Add mem ops support for branch2 clocksTaniya Das2-0/+59
Add the support for mem ops implementation to handle the sequence of enable/disable of the memories in ethernet PHY, prior to enable/disable of the respective clocks, which helps retain the respecive block's register contents. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-3-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: gpucc-sm8150: Update the gpu_cc_pll1 configSatya Priya Kakitapalli1-2/+2
Update the test_ctl_hi_val and test_ctl_hi1_val of gpu_cc_pll1 as per latest HW recommendation. Fixes: 0cef71f2ccc8 ("clk: qcom: Add graphics clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231122042814.4158076-1-quic_skakitap@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: rpmh: add clocks for SM8650Neil Armstrong1-0/+34
Add RPMH Clocks for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-11-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 GPU Clock Controller driverNeil Armstrong3-0/+670
Add Graphics Clock Controller (GPUCC) support for SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-10-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 Display Clock Controller driverNeil Armstrong3-0/+1821
Add Display Clock Controller (DISPCC) support for SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-9-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 TCSR Clock Controller driverNeil Armstrong3-0/+191
Add TCSR Clock Controller support for SM8650 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-8-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 Global Clock Controller driver, part 2Neil Armstrong3-0/+345
Add Global Clock Controller (GCC) driver plumbing for the SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-7-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: add the SM8650 Global Clock Controller driver, part 1Neil Armstrong1-0/+3514
Add Global Clock Controller (GCC) tables for the SM8650 platform, the driver plumbing will be added afterwards. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-6-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: gcc-msm8939: Add missing CSI2 related clocksVincent Knecht1-3/+107
When adding in the indexes for this clock-controller we missed GCC_CAMSS_CSI2_AHB_CLK, GCC_CAMSS_CSI2_CLK, GCC_CAMSS_CSI2PHY_CLK, GCC_CAMSS_CSI2PIX_CLK and GCC_CAMSS_CSI2RDI_CLK. Add them in now and rename ftbl_gcc_camss_csi0_1_clk to account for csi2 also using it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20231029061948.505883-2-vincent.knecht@mailoo.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCCBryan O'Donoghue3-0/+3054
Add the sc8280xp CAMCC driver which follows the sdm845 CAMCC lineage with additional CCI and IFE blocks and more granular clock parentage. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231026105345.3376-4-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-03clk: qcom: apss-ipq-pll: add support for IPQ5018Gokul Sriram Palanisamy1-0/+21
IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets, add configuration values and the compatible. Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230925102826.405446-3-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-11-28clk: qcom: Fix SM_CAMCC_8550 dependenciesJagadeesh Kona1-0/+1
SM_GCC_8550 depends on ARM64 but it is selected by SM_CAMCC_8550, which should have the same dependencies as SM_GCC_8550 to avoid the below Kconfig warning reported by kernel test robot. WARNING: unmet direct dependencies detected for SM_GCC_8550 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n]) Selected by [y]: - SM_CAMCC_8550 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311062309.XugQH7AH-lkp@intel.com/ Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Link: https://lore.kernel.org/r/20231107064545.13120-1-quic_jkona@quicinc.com Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-31Merge branch 'clk-cleanup' into clk-nextStephen Boyd6-48/+22
* clk-cleanup: clk: si521xx: Increase stack based print buffer size in probe clk: Use device_get_match_data() clk: cdce925: Extend match support for OF tables clk: si570: Simplify probe clk: si5351: Simplify probe clk: rs9: Use i2c_get_match_data() instead of device_get_match_data() clk: clk-si544: Simplify probe() and is_valid_frequency() clk: si521xx: Use i2c_get_match_data() instead of device_get_match_data() clk: npcm7xx: Fix incorrect kfree clk: at91: remove unnecessary conditions clk: ti: fix double free in of_ti_divider_clk_setup() clk: keystone: pll: fix a couple NULL vs IS_ERR() checks clk: ralink: mtmips: quiet unused variable warning clk: gate: fix comment typo and grammar clk: asm9620: Remove 'hw' local variable that isn't checked
2023-10-24clk: Use device_get_match_data()Rob Herring6-48/+22
Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231006213959.334439-1-robh@kernel.org Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #msm part Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # Samsung Acked-by: David Lechner <david@lechnology.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-21clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock providerKathiravan Thirumoorthy1-0/+3
While the kernel is booting up, APSS PLL will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured and select the rate based on the opp table and the source will be changed to APSS_PLL_EARLY. Without this patch, CPU Freq driver reports that CPU is running at 24MHz instead of the 800MHz. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-7-c8ceb1a37680@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 11:59:29 +0300