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path: root/drivers/clk/nxp
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2016-11-02clk: nxp: clk-lpc18xx-ccu: Unmap region obtained by of_iomapArvind Yadav1-1/+4
Free memory mapping, if lpc18xx_ccu_init() is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: lpc32xx: add a quirk for PWM and MS clock dividersVladimir Zapolskiy1-4/+28
In common clock framework CLK_DIVIDER_ONE_BASED or'ed with CLK_DIVIDER_ALLOW_ZERO flags indicates that 1) a divider clock may be set to zero value, 2) divider's zero value is interpreted as a non-divided clock. On the LPC32xx platform clock dividers of PWM and memory card clocks comply with the first condition, but zero value means a gated clock, thus it may happen that the divider value is not updated when the clock is enabled and the clock remains gated. The change adds one-shot quirks, which check for zero value of divider on initialization and set it to a non-zero value, therefore in runtime a gate clock will work as expected. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-21clk: nxp: clk-lpc32xx: Unmap region obtained by of_iomapArvind Yadav1-0/+1
Free memory mapping, if lpc32xx_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-13clk: nxp: Use new macro CLK_OF_DECLARE_DRIVERRicardo Ribalda Delgado1-1/+2
This driver initializes a clock provider via lpc18xx_creg_clk_init and then continues the initialization on lpc18xx_creg_clk_probe. Use the new macro to notify the clk subsystem about this behaviour. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> [sboyd@codeaurora.org: s/npx/nxp/ in subject] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-07clk: lpc32xx: allow peripheral clock selection in device treeSylvain Lemieux1-2/+1
This patch add the support to select the peripheral clock (PERIPH) as a parent clock source using the "assigned-clock-parents" parameter in the device tree. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1464982475-24738-1-git-send-email-slemieux.tyco@gmail.com
2016-05-06clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0Stephen Boyd1-0/+1
Failure to initialize this flag to 0 by default can result in stack junk filling the clk_init_data structure and weird things happen. Joachim noticed that the critical clk feature started triggering for these clks causing boot failures, when it really shouldn't have happened: BUG: scheduling while atomic: swapper/0/0x00000002 CPU: 0 PID: 0 Comm: swapper Not tainted 4.6.0-rc6-next-20160505-00001-g5c8320450d1c #826 Hardware name: NXP LPC18xx/43xx (Device Tree) [<2800be81>] (unwind_backtrace) from [<2800b22f>] (show_stack+0xb/0xc) [<2800b22f>] (show_stack) from [<2801ea21>] (__schedule_bug+0x2d/0x44) [<2801ea21>] (__schedule_bug) from [<281dc937>] (__schedule+0x3b/0x268) [<281dc937>] (__schedule) from [<281dcbbb>] (schedule+0x57/0x64) [<281dcbbb>] (schedule) from [<281de8ef>] (schedule_timeout+0xfb/0x120) [<281de8ef>] (schedule_timeout) from [<28030fcd>] (msleep+0xf/0x12) [<28030fcd>] (msleep) from [<28165a6d>] (clk_creg_32k_prepare+0x1f/0x24) [<28165a6d>] (clk_creg_32k_prepare) from [<281620d5>] (clk_core_prepare+0x1d/0x36) [<281620d5>] (clk_core_prepare) from [<2816340b>] (clk_register+0x22f/0x318) [<2816340b>] (clk_register) from [<282b06c9>] (lpc18xx_creg_clk_init+0x55/0x84) [<282b06c9>] (lpc18xx_creg_clk_init) from [<282b0149>] (of_clk_init+0xc1/0x12c) [<282b0149>] (of_clk_init) from [<282a665d>] (time_init+0x15/0x20) [<282a665d>] (time_init) from [<282a457d>] (start_kernel+0x169/0x274) [<282a457d>] (start_kernel) from [<28008025>] (0x28008025) bad: scheduling from the idle thread! CPU: 0 PID: 0 Comm: swapper Tainted: G W 4.6.0-rc6-next-20160505-00001-g5c8320450d1c #826 Fix this by initializing the flags member to 0. Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04clk: add lpc18xx creg clk driverJoachim Eastwood2-0/+227
The CREG block on lpc18xx contains configuration register for two low power clocks. Support enabling of these two clocks with a clk driver that access CREG trough the syscon regmap interface. These clocks are needed to support peripherals like the internal RTC on lpc18xx. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03clk: lpc32xx: fix compilation warningSylvain Lemieux1-1/+4
Remove the following false positives compilation warning: - drivers/clk/nxp/clk-lpc32xx.c: In function 'lpc32xx_clk_register': warning: 'hw' may be used uninitialized in this function [-Wmaybe-uninitialized] - drivers/clk/nxp/clk-lpc32xx.c: In function 'clk_hclk_pll_round_rate': warning: 'p' may be used uninitialized in this function [-Wmaybe-uninitialized] warning: 'n' may be used uninitialized in this function [-Wmaybe-uninitialized] warning: 'm' may be used uninitialized in this function [-Wmaybe-uninitialized] Tested using gcc version 4.7.3. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> [sboyd@codeaurora.org: Drop assignment of hw to NULL as return silences it and is less likely to lead to hiding problems later] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03clk: nxp: Remove CLK_IS_ROOTStephen Boyd1-1/+1
This flag is a no-op now. Remove usage of the flag. Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10clk: lpc32xx: add HCLK PLL output configurationSylvain Lemieux1-5/+1
This patch add the support to setup the HCLK PLL output using the "assigned-clock-rates" parameter in the device tree. If the option is not use, the clock setup by the kickstart and/or bootloader remain unchanged. The previous kernel version did not change the clock frequency output setup by the kickstart and/or bootloader; this version always setup the clock frequency output to 208MHz. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10clk: lpc32xx: do not register clock "0"Sylvain Lemieux1-2/+2
The following errors are display in the console during the power-on: [ 0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12 [ 0.000000] lpc32xx_clk_init: failed to register (null) clock: -12 There is no need to register clock "0"; the first clock used is 1; Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> [sboyd@codeaurora.org: s/prepare/register/] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang1-2/+0
to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk-divider: make sure read-only dividers do not write to their registerHeiko Stuebner1-1/+1
Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-24clk: lpc32xx: add common clock framework driverVladimir Zapolskiy2-0/+1570
Add support for all configurable clocks found on NXP LPC32xx SoC. The list contains several heterogenous groups of clocks: * system clocks including multiple dividers and muxes, * x397 PLL, HCLK PLL and USB PLL, * peripheral clocks inherited from rtc, hclk and pclk, * USB controller clocks: AHB slave, I2C, OTG, OHCI and device. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-10-26clk: lpc18xx-cgu: fix potential system hang when disabling unused clocksJoachim Eastwood1-3/+39
The clock consumer (CCU) of the CGU must be able to check if a CGU base clock is really running since access to the CCU registers requires a running base clock. Access with a disabled base clock will cause the system to hang. Fix this issue by adding code that check if the parent clock is running in the is_enabled clk_ops callback. Since certain clocks can be cascaded this must be added to all clock gates. The hang would occur if the boot ROM or boot loader didn't setup and enable the USB0 clock. Then when the clk framework tried to access the CCU register it would hang the system. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-26clk: lpc18xx-ccu: fix potential system hang when disabling unused clocksJoachim Eastwood1-2/+15
CCU branch clock register must only be accessed while the base (parent) clock is running. Access with a disabled base clock will cause the system to hang. Fix this issue by adding code that check if the parent clock is running in the is_enabled clk_ops callback. This hang would occur when disabling unused clocks after AMBA runtime pm had already disabled some of the clocks. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: nxp: Remove clk.h includeStephen Boyd1-1/+0
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the include here because this is a provider driver. Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-19clk: add lpc18xx ccu clk driverJoachim Eastwood2-0/+294
Add driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU provides fine grained gating of most clocks present in the SoC. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-19clk: add lpc18xx cgu clk driverJoachim Eastwood2-0/+636
Add driver for NXP LPC18xx/43xx Clock Generation Unit (CGU). The CGU contains several clock generators and output stages that route the clocks either directly to peripherals or to a Clock Control Unit (CCU). Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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