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path: root/drivers/clk/meson
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2018-03-13clk: meson: add regmap to the clock controllersJerome Brunet4-12/+52
This change registers a regmap in meson8b, gxbb and axg controllers. The clock are still accessing their registers directly through iomem. Once all clocks handled by these controllers have been move to regmap, the regmap register will be removed and replaced with a syscon request. This is needed because other drivers, such as the HDMI driver, need to access the HHI register region Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: remove superseded aoclk_gate_regmapJerome Brunet2-56/+0
aoclk_gate_regmap has been replaced by meson's clk_regmap. It is no longer necessary so, remove it Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: switch gxbb ao_clk to clk_regmapJerome Brunet4-12/+12
Drop the gxbb ao specific regmap based clock and use the meson clk_regmap based clock instead. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: add regmap clocksJerome Brunet4-0/+282
Meson clock controllers need to move the classical iomem registers to regmap. This is triggered because the HHI controllers found on the GXBB and GXL host more than just clocks. To properly handle this, we would like to migrate HHI to syscon. Also GXBB AO clock controller already use regmap, AXG AO and Audio clock controllers will as well. The purpose of this change is to provide a common structure to these meson controllers (and possibly others) for regmap based clocks. This change provides the basic gate, mux and divider, based on the helpers provided by the related generic clocks Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: remove obsolete commentsJerome Brunet3-12/+0
Over time things changes in CCF and issues have been fixed in meson controllers. Now, clk81 is decently modeled by read-only PLLs, a mux, a divider and a gate. We can remove the FIXME comments related to clk81. Also remove the comment about devm_clk_hw_register, as there is apparently nothing wrong with it. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: only one loop index is necessary in probeJerome Brunet3-15/+14
We don't need several loop index variables in the probe function This is far from being critical but since we are doing a vast rework of meson clock controllers, now is the time to lower the entropy a bit Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: use devm_of_clk_add_hw_providerJerome Brunet3-6/+7
There is no remove callbacks in meson's clock controllers and of_clk_del_provider is never called if of_clk_add_hw_provider has been executed, introducing a potential memory leak. Fixing this by the using the devm variant. In reality, the leak would never happen since these controllers are never unloaded once in use ... still, this is worth cleaning. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: use dev pointer where possibleJerome Brunet2-5/+5
The 'dev' pointer is directly available in gxbb and axg clock controller, so consistently use it instead of going the through the 'pdev' pointer once in while Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-02-12clk: meson: add axg misc bit to the mpll driverJerome Brunet3-0/+28
On axg, the rate of the mpll is stuck as if sdm value was 4 and could not change (expect for mpll2 strangely). Looking at the vendor kernel, it turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register is required. Setting this bit solves the problem and the mpll rates are back to normal Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: axg: fix the od shift of the sys_pllYixun Lan1-1/+1
According to the datasheet, the od shift of sys_pll is actually 16. Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers') Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> [fixed commit message] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: axg: add the fractional part of the fixed_pllJerome Brunet1-0/+5
The fixed_pll also has a fractional part. On axg s400 board, without this parameter, the calculated rate is off by ~8Mhz (0,4%). The fixed_pll being the root of the peripheral clock tree, this error is propagated to the rest of the clocks Adding the definition of the parameter fixes the problem Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: gxbb: add the fractional part of the fixed_pllJerome Brunet1-0/+5
The fixed_pll of gxbb and gxl also has a fractional parameter. This has not been a problem so far because the fractional part is actually set to 0 on these platforms, so the rate remains correct when it is ignored. Still, it is better represent the pll the way it is, so add the frac parameter now Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: fix rate calculation of plls with a fractional partJerome Brunet3-3/+15
The rate of the parent should not be multiplied by 2 when the pll has a fractional part. This is making the rate calculation of the gxl_hdmi_pll wrong (and others as well). This multiplication is specific to the hdmi_pll of gxbb and is most likely due to a multiplier sitting in front of this particular pll. Add a fixed factor clock in front on the gxbb pll and remove this constant from the calculation to fix the problem Fixes: 4a47295144dd ("clk: meson: fractional pll support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: add the gxl hdmi pllJerome Brunet1-2/+48
The hdmi pll used in the gxl family is actually different from the gxbb one. The register layout is completely different, which explain why the hdmi pll rate has always been rubbish on the gxl family. Adding the correct register field is the first part of the fix to get a correct rate out the hdmi pll Fixes: 0d48fc558d01 ("clk: meson-gxbb: Add GXL/GXM GP0 Variant") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: add od3 to the pll driverJerome Brunet3-3/+23
Some meson plls, such as the hdmi pll, are using a 3rd od parameter, which is yet another "power of 2" post divider. Add it to fix the calculation of the hdmi_pll rate Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: use the frac parameter width instead of a constantJerome Brunet1-1/+1
Use the fractional part width in the calculation instead of 12, which happens to be the witdh right now. This is safer in case the field width ever change in the future Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: remove unnecessary rounding in the pll clockJerome Brunet1-8/+9
The pll driver performs the rate calculation in Mhz, which adds an unnecessary rounding down to the Mhz of the rate. Use 64bits long integers to perform this calculation safely on meson8b and perform the calculation in Hz instead Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: remove useless pll rate params tablesJerome Brunet2-188/+0
Read-only plls don't need param table to recalculate the rate. Providing them with a param table is just a waste of memory. Remove the useless tables from sys_pll on gxbb and axg. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-02-12clk: meson: check pll rate param table before using itJerome Brunet1-0/+10
Make sure the rate param table is available before using it. Some read-only plls don't provide it, which is ok since the table is not used by read-only clocks. R/W clocks are supposed to provide it, but it does not hurt check it. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-01-11clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()weiyongjun (A)1-0/+2
platform_get_resource() may return NULL, add proper check to avoid potential NULL dereferencing. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-03Merge tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson ↵Stephen Boyd1-1/+1
into clk-meson Pull Amlogic clk driver update from Jerome Brunet: - Fix overflow in the mpll driver on 32bits arch * tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson: clk: meson: mpll: use 64-bit maths in params_from_rate
2017-12-28clk: meson-axg: make local symbol axg_gp0_params_table staticweiyongjun (A)1-1/+1
Fixes the following sparse warning: drivers/clk/meson/axg.c:260:25: warning: symbol 'axg_gp0_params_table' was not declared. Should it be static? Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: meson-axg: fix return value check in axg_clkc_probe()weiyongjun (A)1-1/+1
In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-24clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl1-1/+1
"rem * SDM_DEN" can easily overflow on the 32-bit Meson8 and Meson8b SoCs if the "remainder" (after the division operation) is greater than 262143Hz. This is likely to happen since the input clock for the MPLLs on Meson8 and Meson8b is "fixed_pll", which is running at a rate of 2550MHz. One example where this was observed to be problematic was the Ethernet clock calculation (which takes MPLL2 as input). When requesting a rate of 125MHz there is a remainder of 2500000Hz. The resulting MPLL2 rate before this patch was 127488329Hz. The resulting MPLL2 rate after this patch is 124999103Hz. Commit b609338b26f5 ("clk: meson: mpll: use 64bit math in rate_from_params") already fixed a similar issue in rate_from_params. Fixes: 007e6e5c5f01d3 ("clk: meson: mpll: add rw operation") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-12-14clk: meson-axg: add clock controller driversQiufang Dai4-0/+1071
Add clock controller drivers for Amlogic Meson-AXG SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-12-14clk: meson: make the spinlock naming more specificYixun Lan3-69/+69
Make the spinlock more specific, so better for lockdep debugging and ctags/grep. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-12-08clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocksJerome Brunet1-13/+3
Remove CLK_IGNORE_UNUSED from mmc clocks. This was only needed while the mmc driver incorrectly used the xtal as source instead of the mmc clock. Now, the driver takes the correct clock, CCF is aware that the clock is being used and we can remove this flag. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com>
2017-11-27clk: meson: gxbb: fix wrong clock for SARADC/SANAYixun Lan1-2/+2
According to the datasheet, in Meson-GXBB/GXL series, The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. Test passed at gxl-s905x-p212 board. The following published datasheets are wrong and should be updated [1] GXBB v1.1.4 [2] GXL v0.3_20170314 Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Tested-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-10-20clk: meson: gxbb: Add VPU and VAPB clocks dataNeil Armstrong1-0/+292
The Amlogic Meson GX SoCs needs these two clocks to power up the VPU power domain. These two clocks are similar to the MALI clocks by having a glitch-free mux and two similar clocks with gate, divider and muxes. Acked-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: removed the CLK_IGNORE_UNUSED on muxes and dividers] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-10-20clk: meson: gxbb: Add VPU and VAPB clockidsNeil Armstrong1-1/+5
Add the clkids for the clocks feeding the Video Processing Unit. Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-24Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into ↵Stephen Boyd10-251/+685
clk-next Pull Amlogic clock driver updates from Neil Armstrong: * meson8b: add the reset controller to the clkc * meson: expose all clk ids * gxbb-aoclk: Add CEC 32k clock * gxbb: add mmc input 0 clocks * meson: fix protection against undefined clks * gxbb: fix audio divider flags * tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson: clk: meson: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb-aoclk: Switch to regmap for register access dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings clk: meson: gxbb: Add sd_emmc clk0 clocks clk: meson: gxbb: fix clk_mclk_i958 divider flags clk: meson: gxbb: fix meson cts_amclk divider flags clk: meson: meson8b: register the built-in reset controller dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller
2017-08-04clk: meson: gxbb-aoclk: Add CEC 32k clockNeil Armstrong4-2/+231
The CEC 32K AO Clock is a dual divider with dual counter to provide a more precise 32768Hz clock for the CEC subsystem from the external xtal. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb-aoclk: Switch to regmap for register accessNeil Armstrong4-23/+95
Switch the aoclk driver to use the new bindings and switch all the registers access to regmap only. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clocksJerome Brunet1-0/+177
Input source 0 of the mmc controllers is not directly xtal, as currently described in DT. Each controller is fed by a composite clock (the usual mux, divider and gate). The muxes inputs are the xtal (default) and the fclk_div clocks. These parents, along with the divider, should be able to provide the necessary rates for mmc and nand operation. The input muxes should also be able to take mpll2, mpll3 and gp0_pll but these are precious clocks, needed for other usage. It is better if the mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is not listed among the possible parents. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: fix clk_mclk_i958 divider flagsJerome Brunet1-3/+4
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 3c277c247eab ("clk: meson: gxbb: add cts_mclk_i958") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: fix meson cts_amclk divider flagsJerome Brunet1-1/+2
CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 4087bd4b2170 ("clk: meson: gxbb: add cts_amclk") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl3-13/+156
The clock controller also includes some reset lines. This patch implements a reset controller to assert and de-assert these resets. The reset controller itself is registered early (through CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot process (to start the secondary CPU cores). According to the public S805 datasheet there are two more reset bits in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by this patch (as these seem to be unused in Amlogic's vendor Linux kernel sources and their u-boot tree): - bit 15: GEN_DIV_SOFT_RESET - bit 14: SOFT_RESET All information was taken from the public S805 Datasheet and Amlogic's vendor GPL kernel sources. This patch is based on an earlier version submitted by Carlo Caione. Suggested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clkidsJerome Brunet1-2/+8
Add the clkids for the clocks feeding the input0 of the mmc controllers Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson-gxbb: expose almost every clock in the bindingsJerome Brunet1-110/+7
Expose all clocks which maybe used as DT bindings Only clock ids internal the controller remain un-exposed Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson8b: expose every clock in the bindingsJerome Brunet1-99/+4
Expose all clocks which maybe used as DT bindings Only clock ids internal the controller remain un-exposed (none on this particular controller at the moment) Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: gxbb: fix protection against undefined clksJerome Brunet1-0/+2
gxbb clock driver gracefully handles case where the clkid is defined but the clock hw pointer is not provided, as long as it is not at the end of the hw_onecell_data array. This patch ensure that the last entries are defined as well to handle this particular case. Fixes: a70c6e06ed7c ("clk: meson: gxbb: protect against holes in the onecell_data array") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04clk: meson: meson8b: fix protection against undefined clksJerome Brunet1-0/+1
meson8b clock driver gracefully handles case where the clkid is defined but the clock hw pointer is not provided, as long as it is not at the end of the hw_onecell_data array. This patch ensure that the last entries are defined as well to handle this particular case. Fixes: e92f7cca446e ("clk: meson8b: clean up fixed rate clocks") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet4-0/+18
mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-06-17Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ↵Stephen Boyd4-19/+25
clk-next Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
2017-06-16clk: meson: gxbb: add all clk81 parentsJerome Brunet1-5/+8
Remove the FIXME on clk81 mux and add all the documented parents Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-16Merge branch 'next/headers' into next/driversJerome Brunet1-10/+10
2017-06-12clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl2-4/+7
The clock controller on Meson8, Meson8b and Meson8m2 is very similar based on the code from the Amlogic GPL kernel sources. Add separate compatibles for each SoC to make sure that we can easily implement all the small differences for each SoC later on. In general the Meson8 and Meson8m2 seem to be almost identical as they even share the same mach-meson8 directory in Amlogic's GPL kernel sources. The main clocks on Meson8, Meson8b and Meson8m2 are very similar, because they are all using the same PLL values, 90% of the clock gates are the same (the actual diffstat of the mach-meson8/clock.c and mach-meson8b/clock.c files is around 30 to 40 lines, when excluding all commented out code). The difference between the Meson8 and Meson8b clock gates seem to be: - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, CSI_DIG_CLKIN gates which don't seem to be available on Meson8b - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead of "PERIPHS_TOP" (on Meson8b) - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL kernel sources) None of these gates is added for now, since it's unclear whether these definitions are actually correct (the VCLK2_ENCT gate for example is defined, but only used in some commented block). The main difference between all three SoCs seem to be the video (VPU) clocks. Apart from different supported clock rates (according to vpu.c in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the most notable difference is that Meson8m2 has a GP_PLL clock and a mux (probably the same as on the Meson GX SoCs) to support glitch-free (clock rate) switching. None of these VPU clocks are not supported by our mainline meson8b clock driver yet though. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12clk: meson8b: export the ethernet gate clockMartin Blumenstingl1-1/+1
Export the ethernet gate clock to the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12clk: meson8b: export the USB clocksMartin Blumenstingl1-5/+5
Export the USB related clocks (for the USB controller and the USB2 PHYs) so they can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12clk: meson8b: export the gate clock for the HW random number generatorMartin Blumenstingl1-1/+1
This exports the clock so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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