kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-03-25	clk: meson: pll: fix rounding and setting a rate that matches precisely	Martin Blumenstingl	1	-1/+1
2019-03-19	clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id	Neil Armstrong	1	-1/+0
2019-03-19	clk: meson-g12a: fix VPU clock parents	Neil Armstrong	1	-1/+1
2019-03-19	clk: meson: g12a: fix VPU clock muxes mask	Maxime Jourdan	1	-2/+2
2019-03-19	clk: meson-gxbb: round the vdec dividers to closest	Maxime Jourdan	1	-0/+2
2019-02-13	clk: meson: meson8b: fix the naming of the APB clocks	Martin Blumenstingl	2	-14/+14
2019-02-13	clk: meson: Add G12A AO Clock + Reset Controller	Neil Armstrong	4	-1/+491
2019-02-04	clk: meson: factorise meson64 peripheral clock controller drivers	Jerome Brunet	7	-176/+313
2019-02-04	clk: meson: g12a: add peripheral clock controller	Jian Hu	5	-2/+2594
2019-02-04	clk: meson: pll: update driver for the g12a	Jerome Brunet	2	-59/+154
2019-02-02	clk: meson: rework and clean drivers dependencies	Jerome Brunet	29	-281/+465
2019-02-02	clk: meson: axg-audio does not require syscon	Jerome Brunet	1	-1/+1
2019-01-18	clk: meson: ao-clkc: claim clock controller input clocks from DT	Jerome Brunet	4	-14/+82
2019-01-18	clk: meson: axg: claim clock controller input clock from DT	Jerome Brunet	1	-8/+19
2019-01-18	clk: meson: gxbb: claim clock controller input clock from DT	Jerome Brunet	1	-13/+24
2019-01-07	clk: meson: meson8b: add the GPU clock tree	Martin Blumenstingl	2	-1/+154
2019-01-07	clk: meson: meson8b: use a separate clock table for Meson8	Martin Blumenstingl	1	-6/+197
2019-01-07	clk: meson: axg-ao: add 32k generation subtree	Jerome Brunet	2	-25/+163
2019-01-07	clk: meson: gxbb-ao: replace cec-32k with the dual divider	Jerome Brunet	4	-262/+204
2019-01-07	clk: meson: add dual divider clock driver	Jerome Brunet	3	-1/+150
2019-01-07	clk: meson: clean-up clock registration	Jerome Brunet	1	-5/+10
2018-12-15	Merge branch 'clk-fixes' into clk-next	Stephen Boyd	2	-0/+25
2018-12-13	Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl...	Stephen Boyd	7	-71/+870
2018-12-11	clk: meson: axg-audio: use the clk input helper function	Jerome Brunet	1	-59/+24
2018-12-05	clk: meson: add clk-input helper function	Jerome Brunet	3	-0/+50
2018-12-04	clk: meson: Mark some things static	Stephen Boyd	2	-6/+6
2018-12-03	clk: meson: meson8b: add the read-only video clock trees	Martin Blumenstingl	2	-10/+782
2018-12-03	clk: meson: meson8b: add the fractional divider for vid_pll_dco	Martin Blumenstingl	2	-0/+6
2018-12-03	clk: meson: meson8b: fix the offset of vid_pll_dco's N value	Martin Blumenstingl	1	-1/+1
2018-11-27	clk: meson: Fix GXL HDMI PLL fractional bits width	Neil Armstrong	1	-1/+7
2018-11-23	clk: meson: meson8b: add the CPU clock post divider clocks	Martin Blumenstingl	2	-1/+256
2018-11-23	clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3	Martin Blumenstingl	2	-12/+12
2018-11-23	clk: meson: clk-regmap: add read-only gate ops	Martin Blumenstingl	2	-0/+6
2018-11-23	clk: meson: meson8b: allow changing the CPU clock tree	Martin Blumenstingl	1	-6/+6
2018-11-23	clk: meson: meson8b: run from the XTAL when changing the CPU frequency	Martin Blumenstingl	1	-0/+63
2018-11-23	clk: meson: meson8b: add support for more M/N values in sys_pll	Martin Blumenstingl	1	-0/+5
2018-11-23	clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL	Martin Blumenstingl	1	-1/+2
2018-11-23	clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel	Martin Blumenstingl	1	-2/+9
2018-11-23	clk: meson: clk-pll: check if the clock is already enabled	Martin Blumenstingl	1	-0/+19
2018-11-23	clk: meson: meson8b: fix the width of the cpu_scale_div clock	Martin Blumenstingl	1	-1/+1
2018-11-23	clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table	Martin Blumenstingl	1	-7/+8
2018-11-23	clk: meson: meson8b: use the HHI syscon if available	Martin Blumenstingl	1	-9/+15
2018-11-23	clk: meson-gxbb: Add video clocks	Neil Armstrong	1	-0/+722
2018-11-23	dt-bindings: clk: meson-gxbb: Add Video clock bindings	Neil Armstrong	1	-2/+24
2018-11-23	clk: meson-gxbb: Fix HDMI PLL for GXL SoCs	Neil Armstrong	1	-2/+49
2018-11-23	clk: meson: Add vid_pll divider driver	Neil Armstrong	3	-1/+98
2018-11-08	clk: meson: axg: mark fdiv2 and fdiv3 as critical	Jerome Brunet	1	-0/+13
2018-11-08	clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL	Christian Hewitt	1	-0/+12
2018-09-26	clk: meson: meson8b: use the regmap in the internal reset controller	Martin Blumenstingl	1	-7/+6
2018-09-26	clk: meson: meson8b: register the clock controller early	Martin Blumenstingl	1	-60/+34