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path: root/drivers/clk/meson/gxbb.c
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2023-08-31Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd1-424/+424
2023-08-08clk: meson: eeclk: move bindings include to main driverNeil Armstrong1-0/+2
2023-08-08clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong1-424/+422
2023-07-19clk: Explicitly include correct DT includesRob Herring1-1/+1
2021-11-30clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBBMartin Blumenstingl1-3/+41
2020-11-23clk: meson: enable building as modulesKevin Hilman1-1/+4
2020-04-16clk: meson: gxbb: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl1-18/+22
2020-02-13clk: meson: gxbb: set audio output clock hierarchyJerome Brunet1-8/+10
2020-02-13clk: meson: gxbb: add the gxl internal dac gateJerome Brunet1-0/+3
2019-10-01clk: meson: gxbb: let sar_adc_clk_div set the parent clock rateMartin Blumenstingl1-0/+1
2019-07-29clk: meson: clk-regmap: migrate to new parent description methodAlexandre Mergnat1-0/+3
2019-07-29clk: meson: gxbb: migrate to the new parent description methodAlexandre Mergnat1-203/+451
2019-05-20clk: meson: gxbb: no spread spectrum on mpll0Jerome Brunet1-5/+0
2019-03-19clk: meson-gxbb: round the vdec dividers to closestMaxime Jourdan1-0/+2
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet1-75/+197
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet1-1/+4
2019-01-18clk: meson: gxbb: claim clock controller input clock from DTJerome Brunet1-13/+24
2018-12-15Merge branch 'clk-fixes' into clk-nextStephen Boyd1-0/+12
2018-12-13Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl...Stephen Boyd1-1/+7
2018-12-04clk: meson: Mark some things staticStephen Boyd1-4/+4
2018-11-27clk: meson: Fix GXL HDMI PLL fractional bits widthNeil Armstrong1-1/+7
2018-11-23clk: meson-gxbb: Add video clocksNeil Armstrong1-0/+722
2018-11-23clk: meson-gxbb: Fix HDMI PLL for GXL SoCsNeil Armstrong1-2/+49
2018-11-08clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICALChristian Hewitt1-0/+12
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet1-60/+60
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet1-256/+228
2018-09-26clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet1-4/+8
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet1-2/+30
2018-07-09clk: meson: add gen_clkJerome Brunet1-0/+66
2018-07-09clk: meson: stop rate propagation for audio clocksJerome Brunet1-9/+7
2018-07-09clk: meson: remove obsolete register accessJerome Brunet1-34/+2
2018-06-19clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICALNeil Armstrong1-0/+1
2018-05-18clk: meson: use SPDX license identifiers consistentlyJerome Brunet1-14/+1
2018-05-15clk: meson: gxbb: add the video decoder clocksMaxime Jourdan1-0/+114
2018-03-15clk: meson: Drop unused local variable and add staticStephen Boyd1-2/+2
2018-03-13clk: meson: clean-up clk81 clocksJerome Brunet1-4/+2
2018-03-13clk: meson: add fdiv clock gatesJerome Brunet1-10/+90
2018-03-13clk: meson: add mpll pre-dividerJerome Brunet1-3/+20
2018-03-13clk: meson: add gp0 frac parameter for axg and gxlJerome Brunet1-1/+6
2018-03-13clk: meson: remove special gp0 lock loopJerome Brunet1-1/+0
2018-03-13clk: meson: poke pll CNTL lastJerome Brunet1-2/+2
2018-03-13clk: meson: use hhi syscon if availableJerome Brunet1-11/+28
2018-03-13clk: meson: split divider and gate part of mpllJerome Brunet1-21/+57
2018-03-13clk: meson: migrate plls clocks to clk_regmapJerome Brunet1-185/+239
2018-03-13clk: meson: migrate the audio divider clock to clk_regmapJerome Brunet1-21/+9
2018-03-13clk: meson: migrate mplls clocks to clk_regmapJerome Brunet1-84/+77
2018-03-13clk: meson: migrate muxes to clk_regmapJerome Brunet1-160/+150
2018-03-13clk: meson: migrate dividers to clk_regmapJerome Brunet1-109/+108
2018-03-13clk: meson: migrate gates to clk_regmapJerome Brunet1-129/+137
2018-03-13clk: meson: add regmap to the clock controllersJerome Brunet1-10/+23