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2021-07-27clk: mediatek: Add MT8192 audio clock supportChun-Jie Chen1-0/+1
Add MT8192 audio clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-11-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-27clk: mediatek: Add MT8192 basic clocks supportChun-Jie Chen1-0/+1
Add MT8192 basic clock providers, include topckgen, apmixedsys, infracfg and pericfg. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-10-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: mediatek: Add MT8167 clock supportFabien Parent1-0/+6
Add the following clock support for MT8167 SoC: topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, vdecsys. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20200918132303.2831815-2-fparent@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-10Merge tag 'clk-for-linus' of ↵Linus Torvalds1-0/+7
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time around we have four lines of diff in the core framework, removing a function that isn't used anymore. Otherwise the main new thing for the common clk framework is that it is selectable in the Kconfig language now. Hopefully this will let clk drivers and clk consumers be testable on more than the architectures that support the clk framework. The goal is to introduce some Kunit tests for the framework. Outside of the core framework we have the usual set of various driver updates and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the largest addition this time around in terms of lines of code. After that the x86 (Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or upcoming SoCs. After that the dirstat shows the usual suspects working on their SoC support by fixing minor bugs, correcting data and converting some of their DT bindings to YAML. Core: - Allow the COMMON_CLK config to be selectable New Drivers: - Clk driver for Baikal-T1 SoCs - Mediatek MT6765 clock support - Support for Intel Agilex clks - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for the new Renesas RZ/G1H (R8A7742) SoC - Add support for Qualcomm's MSM8939 Generic Clock Controller Updates: - Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - A single minor rounding fix for the legacy Allwinner clock support - A few patches from Abel Vesa as preparation of adding audiomix clock support on i.MX - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3 drivers - Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on aarch64 hardware - A series from Peng Fan to improve i.MX8M clock drivers, using composite clock for core and bus clk slice - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined bit rates - A couple changes for EMC frequency scaling on Tegra210 - Support for CPU frequency scaling on Tegra20/Tegra30 - New clk gate for CSI test pattern generator on Tegra210 - Regression fixes for Samsung exynos542x and exynos5433 SoCs - Use of fallthrough; attribute for Samsung s3c24xx - Updates and fixup HDMI and video clocks on Meson8b - Fixup reset polarity on Meson8b - Fix GPU glitch free mux switch on Meson gx and g12 - A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2 - Two more conversions of Renesas DT bindings to json-schema - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits) clk: mediatek: Remove ifr{0,1}_cfg_regs structures clk: baikal-t1: remove redundant assignment to variable 'divider' clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible" dt-bindings: clock: Add a missing include to MMP Audio Clock binding dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first clk: clk-si5341: Add support for the Si5345 series ...
2020-05-29clk: mediatek: Add MT6765 clock supportOwen Chen1-0/+7
Add MT6765 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Link: https://lore.kernel.org/r/1582278742-1626-6-git-send-email-macpaul.lin@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-04-13clk / soc: mediatek: Move mt8173 MMSYS to platform driverMatthias Brugger1-0/+1
There is no strong reason for this to use CLK_OF_DECLARE instead of being a platform driver. Plus, MMSYS provides clocks but also a shared register space for the mediatek-drm and the mediatek-mdp driver. So move the MMSYS clocks to a new platform driver and also create a new MMSYS platform driver in drivers/soc/mediatek that instantiates the clock driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-09-09clk: mediatek: Add MT6779 clock supportmtk017611-0/+9
Add MT6779 clock support, include topckgen, apmixedsys, infracfg, and subsystem clocks. Signed-off-by: mtk01761 <wendell.lin@mediatek.com> Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07clk: mediatek: add audsys clock driver for MT8516Fabien Parent1-0/+1
Add audsys clock driver for MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-26clk: mediatek: add clock driver for MT8516Fabien Parent1-0/+1
Add the clock driver for the MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11clk: mediatek: Add MT8183 clock supportWeiyi Lu1-0/+12
Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11clk: mediatek: Add new clkmux register APIOwen Chen1-1/+2
On both MT8183 & MT6765, there add "set/clr" register for each clkmux setting, and one update register to trigger value change. It is designed to prevent read-modify-write racing issue. The sw design need to add a new API to handle this hw change with a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> [sboyd@kernel.org: Squash in flags=0 to silence warning] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-11-30clk: mediatek: add clock support for MT7629 SoCRyder Lee1-0/+3
Add all supported clocks exported from every susbystem found on MT7629 SoC. Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-16clk: mediatek: add g3dsys support for MT2701 and MT7623Sean Wang1-0/+1
Add clock driver support for g3dsys on MT2701 and MT7623, which is providing essential clock gate and reset controller to Mali-450. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: mediatek: add audsys support for MT2701Ryder Lee1-0/+1
Add clock driver support for MT2701 audsys. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-01-11clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being builtSean Wang1-2/+1
Changes from v1->v2: Add 'select RESET_CONTROLLER' under COMMON_CLK_MEDIATEK and enable reset.c to be built when COMMON_CLK_MEDIATEK is selected. That should be quite reasonable because the reset controller is tightly embedded inside and exported from these clock subsystems. At least it can be found on infracfg and pericfg subsystem that both are really fundamental block lots of devices must depend on. commit 74cb0d6dde8 ("clk: mediatek: fixup test-building of MediaTek clock drivers") can let the build system looking into the directory where the clock drivers resides and then allow test-building the drivers. But the change also gives rise to certain incorrect behavior which is reset.c being built even not depending on either COMPILE_TEST or ARCH_MEDIATEK alternative dependency. To get rid of reset.c being built unexpectedly on the other platforms, it would be a good change that the file should be built depending on its own specific configuration rather than just on generic RESET_CONTROLLER one. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: Jean Delvare <jdelvare@suse.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-11-18Merge tag 'clk-for-linus' of ↵Linus Torvalds1-0/+12
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have two changes to the core framework this time around. The first being a large change that introduces runtime PM support to the clk framework. Now we properly call runtime PM operations on the device providing a clk when the clk is in use. This helps on SoCs where the clks provided by a device need something to be powered on before using the clks, like power domains or regulators. It also helps power those things down when clks aren't in use. The other core change is a devm API addition for clk providers so we can get rid of a bunch of clk driver remove functions that are just doing of_clk_del_provider(). Outside of the core, we have the usual addition of clk drivers and smattering of non-critical fixes to existing drivers. The biggest diff is support for Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch of data. By the way, we're trying something new here where we build the tree up with topic branches. We plan to work this into our workflow so that we don't step on each other's toes, and so the fixes branch can be merged on an as-needed basis. Summary: Core: - runtime PM support for clk providers - devm API for of_clk_add_hw_provider() New Drivers: - Mediatek MT2712 and MT7622 - Renesas R-Car V3M SoC Updates: - runtime PM support for Samsung exynos5433/exynos4412 providers - removal of clkdev aliases on Samsung SoCs - convert clk-gpio to use gpio descriptors - various driver cleanups to match kernel coding style - Amlogic Video Processing Unit VPU and VAPB clks - sigma-delta modulation for Allwinner audio PLLs - Allwinner A83t Display clks - support for the second display unit clock on Renesas RZ/G1E - suspend/resume support for Renesas R-Car Gen3 CPG/MSSR - new clock ids for Rockchip rk3188 and rk3368 SoCs - various 'const' markings on clk_ops structures - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: stm32h7: fix test of clock config clk: pxa: fix building on older compilers clk: sunxi-ng: a83t: Fix i2c buses bits clk: ti: dra7-atl-clock: fix child-node lookups clk: qcom: common: fix legacy board-clock registration clk: uniphier: fix DAPLL2 clock rate of Pro5 clk: uniphier: fix parent of miodmac clock data clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: kona-setup: Delete error messages for failed memory allocations ARC: clk: fix spelling mistake: "configurarion" -> "configuration" clk: cdce925: remove redundant check for non-null parent_name clk: versatile: Improve sizeof() usage clk: versatile: Delete error messages for failed memory allocations clk: ux500: Improve sizeof() usage clk: ux500: Delete error messages for failed memory allocations clk: spear: Delete error messages for failed memory allocations clk: ti: Delete error messages for failed memory allocations clk: mmp: Adjust checks for NULL pointers ...
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-02clk: mediatek: add clock support for MT7622 SoCSean Wang1-0/+4
Add all supported clocks exported from every susbystem found on MT7622 SoC such as topckgen, apmixedsys, infracfg, pericfg , pciessys, ssusbsys, ethsys and audsys. Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-11-02clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com1-0/+8
Add MT2712 clock support, include topckgen, apmixedsys, infracfg, pericfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> [sboyd@codeaurora.org: Static on top_clk_data] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-20clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't workSean Wang1-1/+1
This patch adds CPU multiplexer clocks which are essential for Mediatek cpufreq driver. It would use the CPU clock multiplexer to switch to the intermediate clock source temporarily and then wait for the primary clock changing getting stable. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: mediatek: add clk support for MT6797Kevin-CW Chen1-0/+5
Add MT6797 clock support, include topckgen, apmixedsys, infracfg and subsystem clocks Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-09clk: mediatek: Add MT2701 clock supportShunli Wang1-0/+7
Add MT2701 clock support, include topckgen, apmixedsys, infracfg, pericfg and subsystem clocks. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19clk: mediatek: Refine the makefile to support multiple clock driversJames Liao1-3/+3
Add a Kconfig to define clock configuration for each SoC, and modify the Makefile to build drivers that only selected in config. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao1-1/+1
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock is needed by USB 3.0. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-05-06clk: mediatek: Add basic clocks for Mediatek MT8173.James Liao1-0/+1
This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-06clk: mediatek: Add basic clocks for Mediatek MT8135.James Liao1-0/+1
This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-06clk: mediatek: Add reset controller supportSascha Hauer1-0/+1
The pericfg and infracfg units also provide reset lines to several other SoC internal units. This adds a function which can be called from the pericfg and infracfg initialization functions which will register the reset controller using reset_controller_register. The reset controller will provide support for resetting the units connected to the pericfg and infracfg controller. The units resetted by this controller can use the standard reset device tree binding to gain access to the reset lines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-06clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao1-0/+1
This patch adds common clock support for Mediatek SoCs, including plls, muxes and clock gates. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [sboyd@codeaurora.org: Squelch checkpatch warning in clk-mtk.h] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-01 00:03:57 +0300