| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-01-19 | clk: Add Ingenic jz4770 CGU driver | Paul Cercueil | 2 | -0/+484 |
| 2018-01-19 | clk: ingenic: Add code to enable/disable PLLs | Paul Cercueil | 1 | -15/+74 |
| 2018-01-19 | clk: ingenic: support PLLs with no bypass bit | Paul Cercueil | 2 | -1/+4 |
| 2018-01-19 | clk: ingenic: Fix recalc_rate for clocks with fixed divider | Paul Cercueil | 1 | -0/+2 |
| 2018-01-19 | clk: ingenic: Use const pointer to clk_ops in struct | Paul Cercueil | 2 | -2/+2 |
| 2017-11-03 | Update MIPS email addresses | Paul Burton | 4 | -4/+4 |
| 2016-05-13 | clk: ingenic: Allow divider value to be divided | Harvey Hunt | 4 | -34/+47 |
| 2015-07-20 | clk: ingenic: Include clk.h | Stephen Boyd | 1 | -0/+1 |
| 2015-06-21 | clk: ingenic: add JZ4780 CGU support | Paul Burton | 2 | -0/+734 |
| 2015-06-21 | MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu | Paul Burton | 1 | -0/+37 |
| 2015-06-21 | MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu | Paul Burton | 1 | -0/+22 |
| 2015-06-21 | MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu | Paul Burton | 1 | -0/+22 |
| 2015-06-21 | MIPS,clk: migrate JZ4740 to common clock framework | Paul Burton | 2 | -0/+223 |
| 2015-06-21 | clk: ingenic: add driver for Ingenic SoC CGU clocks | Paul Burton | 3 | -0/+935 |
