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path: root/drivers/clk/clk-fractional-divider.c
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2015-07-28clk: basic-type: Silence warnings about lock imbalancesStephen Boyd1-0/+8
The basic clock types use conditional locking for the register accessor spinlocks. Add __acquire() and __release() markings in the right locations so that sparse isn't tripped up on the conditional locking. drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-15clk: basic-types: Remove useless allocation failure printksStephen Boyd1-3/+1
Printing an error on kmalloc() failures is unnecessary. Remove the print and use *ptr in sizeof() for future-proof code. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-12clk: fractional-divider: support for divider bypassingHeikki Krogerus1-0/+3
If the divider or multiplier values are 0 in the register, bypassing the divider and returning the parent clock rate in clk_fd_recalc_rate(). Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed commitlog typo]
2014-09-10clk: fractional-divider: cast parent_rate to u64 before multiplyingHeiko Stübner1-1/+1
On 32bit architectures, like ARM calculating the fractional rate will do the multiplication before converting the value to u64 when it gets assigned to ret, which can produce overflows. The error in question happened with a parent_rate of 386MHz, m = 3000, n = 60000, which resulted in a wrong rate value of 15812Hz. Therefore cast parent_rate to u64 to make sure the multiplication happens in a 64bit space and produces the correct 192MHz in the example. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-20clk: new basic clk type for fractional dividerHeikki Krogerus1-0/+135
Fractional divider clocks are fairly common. This adds basic type for them. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>