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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
ARM: tegra: Device tree changes for v6.18-rc1
Add DFLL support on Tegra114, fix some issues on Transformer and P880
devices and add support for the ASUS Eee Pad Slider SL101.
* tag 'tegra-for-6.18-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: add support for ASUS Eee Pad Slider SL101
ARM: tegra: transformer-20: fix audio-codec interrupt
ARM: tegra: transformer-20: add missing magnetometer interrupt
ARM: tegra: Add DFLL clock support for Tegra114
ARM: tegra: p880: set correct touchscreen clipping
Link: https://lore.kernel.org/r/20250914063927.89981-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into soc/dt
STi dt fixes:
- Remove unused stih407-clock.dtsi file
* tag 'sti-dt-for-v6.18-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
ARM: dts: sti: remove dangling stih407-clock file
Link: https://lore.kernel.org/r/4a710c05-aeeb-4421-b3a1-5bfb8230d51d@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
mvebu dt64 for 6.18 (part 1)
Improve device tree correctness:
- Whitespace cleanup
- Add missing address-cells
Add new board definition for RIPE Atlas Probe v5, based on Turris MOX
(Armada 3720 SoC)
* tag 'mvebu-dt64-6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
arm64: dts: marvell: cn9130-sr-som: add missing properties to emmc
arm64: dts: marvell: add dts for RIPE Atlas Probe v5
dt-bindings: marvell: armada-37xx: add ripe,atlas-v5 compatible
arm64: dts: marvell: armada-cp11x: Add default ICU address cells
arm64: dts: marvell: armada-37xx: Add default PCI interrup controller address cells
arm64: dts: marvell: Minor whitespace cleanup
Link: https://lore.kernel.org/r/87frcrn1o0.fsf@BLaptop.bootlin.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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soc/dt
arm64: Xilinx DT changes for 6.18
- Fix some issues reported by dtschema
- Properly mark EMMC devices
- Update PSCI version
- Update DP description and enable it on boards
- Disable DEBUG IPs by default
SOM:
- Describe usb hubs
- Fix PWM polarity issue
- Add support for k24, kr260 and kd240
Versal NET:
- Describe CPU cache layout
- Fix RTC calibration value
* tag 'zynqmp-dt-for-6.18' of https://github.com/Xilinx/linux-xlnx:
arm64: versal-net: Describe L1/L2/L3/LLC caches
arm64: zynqmp: Enable DP in kr260/kv260 revA
arm64: zynqmp: Describe ethernet controllers via aliases on SOM
arm64: zynqmp: Revert usb node drive strength and slew rate for zcu106
arm64: zynqmp: Disable coresight by default
arm64: zynqmp: Add support for kd240 board
arm64: zynqmp: Add support for kr260 board
dt-bindings: soc: xilinx: Add support for K24, KR260 and KD240 CCs
arm64: zynqmp: Enable PSCI 1.0
arm64: zynqmp: Enable DP for zcu100, zcu102, zcu104, zcu111
arm64: zynqmp: Introduce DP port labels
arm64: zynqmp: Fix pwm-fan polarity
arm64: zynqmp: Update the usb5744 hub node as per binding
arm64: zynqmp: Add cap-mmc-hw-reset and no-sd, no-sdio property to eMMC
arm64: zynqmp: Remove undocumented arasan,has-mdma property
arm64: zynqmp: Use generic spi@ name in zcu111-revA
arm64: versal-net: Update rtc calibration value
Link: https://lore.kernel.org/r/CAHTX3dK6if9f+-DW5ZEnfSO4=K_Zje-WH-fwysTY77farsSS9g@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.18 (take two)
- Add pin control and I2C support for the RZ/N2H SoC and its
evaluation board,
- Add LED, EEPROM, eMMC, SD card, watchdog, and USB2.0 support for the
RZ/T2H and RZ/N2H SoCs and their evaluation boards,
- Add I3C support for the RZ/V2H and RZ/V2N SoCs,
- Add IMX219 and IMX462 camera overlay support for the Sparrow Hawk
board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (26 commits)
arm64: dts: renesas: sparrow-hawk-fan-pwm: Rework hwmon comment
arm64: dts: renesas: sparrow-hawk: Add overlay for IMX462 on J2
arm64: dts: renesas: sparrow-hawk: Add overlay for IMX462 on J1
arm64: dts: renesas: sparrow-hawk: Add overlay for IMX219 on J2
arm64: dts: renesas: sparrow-hawk: Add overlay for IMX219 on J1
arm64: dts: renesas: rcar: Rename dsi-encoder to dsi
arm64: dts: renesas: r9a09g056: Add I3C node
arm64: dts: renesas: r9a09g057: Add I3C node
arm64: dts: renesas: rzt2h-n2h-evk: Enable USB2.0 support
arm64: dts: renesas: r9a09g047e57-smarc: Use Schmitt input for NMI function
arm64: dts: renesas: r9a09g047e57-smarc: Fix gpio key's pin control node
arm64: dts: renesas: r9a09g047: Enable Tx coe support
arm64: dts: renesas: r9a09g087: Add USB2.0 support
arm64: dts: renesas: r9a09g077: Add USB2.0 support
arm64: dts: renesas: rzt2h-n2h-evk-common: Enable WDT2
arm64: dts: renesas: r9a09g087: Add WDT nodes
arm64: dts: renesas: r9a09g077: Add WDT nodes
arm64: dts: renesas: rzt2h-rzn2h-evk: Enable SD card slot
arm64: dts: renesas: rzt2h-rzn2h-evk: Enable MicroSD card slot
arm64: dts: renesas: rzt2h-rzn2h-evk: Enable eMMC
...
Link: https://lore.kernel.org/r/cover.1757669917.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.18
Add support for Lenovo Thinkbook 16, Dell Inspiron 7441, Dell Latitude
7455, Samsung Galaxy S20, Billion Capture+, the Monaco EVK and the
Lemans EVK.
The SDM845 Cheza development boards are removed, as they are not longer
in use.
For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO
buses are added and the internal GE PHY.
IPQ5424 gets CPU frequency scaling and a missing UART.
The SA8775P SoC is remaned Lemans, to reduce confusion about the chip
name. The IoT memory map introduced and made the default, GDSP FastRPC
and GPR nodes are added.
Touch keys are enabled on the BQ Aquaris X5 Plus.
On QCM2290 the video accelerator is enabled, so is HS timing modes for
eMMC.
The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi
PCIe controller is introduced.
On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is
eMMC support and generic packer router (GPR).
On the Monaco Ride board, the eMMC controller is enabled.
On QRB220 RB1, the venus video accelerator is enabled.
For SC7280 the first PCIe controller and PHY is introduced. SoundWire,
LPASS, and USB offload support is added, the codecs and sound card is
then described on the QCM6490 IDP. The MDSS core reset is introduced, to
clear bootloader configuration on SC7280-based devices.
On Fairphone5, USB audio offload is added.
AudioReach support on SC7280 (QCS6490) is introduced and used to
enable sound on the RB3Gen2 board.
The video clock controller is added to SC8180X.
On SC8280XP the GPI DMA controllers are described and enabled.
Display and GPU is enabled for the Fairphone 3 and charging is enabled
on the Google Pixel 3a.
The routing for the second USB connector on the Lenovo Yoga C630 is
described.
On SM6150 ADSP and CDSP FastRPC is introduced, as is the video
encoder/decoder (venus).
On SM6350 RPMh statistics is enabled, the USB audio offload DAI is
introduced and on Fairphone4 the USB audio offload support is enabled.
On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery
functionality.
On SM8650 ACD levels are added for the GPU.
Camera and video clock controllers power-domains are updated on SM8450,
SM8550, and SM8650, now that support for multiple power-domains is
accepted.
SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes.
The DWC3 glue and core nodes are flattened on a number of platforms.
USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a
variety of platforms, now that the QMP PHY driver supports this.
Platform specific RPMh PD constants are replaced with generic constants
wherever possible.
On X Elite the PM8010 is disabled by default, removing boot splats
on a variety of boards without this PMIC, the video clock controller is
added.
For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is
marked as valid for the external DisplayPorts. The fingerprint reader
found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled.
The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support.
GPU support is added for the X Plus SoC.
* tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (208 commits)
arm64: dts: qcom: x1e80100: Update GPU OPP table
arm64: dts: qcom: sm8650: Drop redundant status from PMK8550 RTC
arm64: dts: qcom: add initial support for Samsung Galaxy S20
dt-bindings: arm: qcom: document x1q board binding
arm64: dts: qcom: sm8250-samsung-r8q: Move common parts to dtsi
arm64: dts: qcom: lemans-evk: Add sound card
arm64: dts: qcom: lemans: Add gpr node
arm64: dts: qcom: x1e78100-t14s-oled: Add eDP panel
arm64: dts: qcom: qcs615-ride: enable venus node to initialize video codec
arm64: dts: qcom: sm6150: add venus node to devicetree
arm64: dts: qcom: x1e80100-romulus: Add WCN7850 Wi-Fi/BT
arm64: dts: qcom: qrb2210-rb1: Enable Venus
arm64: dts: qcom: qcm2290: Add Venus video node
arm64: dts: qcom: monaco-evk: Add sound card
arm64: dts: qcom: qcs8300: Add gpr node
arm64: dts: qcom: qcs8300: Add Monaco EVK board
dt-bindings: arm: qcom: Add Monaco EVK support
arm64: dts: qcom: qcm6490-idp: Add sound card
arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec
arm64: dts: qcom: qcs6490-rb3gen2: Add sound card
...
Link: https://lore.kernel.org/r/20250911233600.3033675-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm32 DeviceTree updates for v6.18
Bring a few updates to the MSM8960 platform and add support for the Sony
Xperia SP.
Touch keys support is added to the Samsung Galaxy Grand 2.
A number of DeviceTree cleanups.
* tag 'qcom-arm32-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: Use GIC_SPI for interrupt-map for readability
ARM: dts: qcom: sdx55: Add default GIC address cells
ARM: dts: qcom: ipq8064: Add default GIC address cells
ARM: dts: qcom: apq8064: Add default GIC address cells
ARM: dts: qcom: ipq4019: Add default GIC address cells
ARM: dts: qcom: apq8064-mako: Minor whitespace cleanup
ARM: dts: qcom: msm8226-samsung-ms013g: Add touch keys
ARM: dts: qcom: msm8974-samsung-hlte: Add touchkey support
ARM: dts: qcom: pm8921: add vibrator device node
ARM: dts: qcom: add device tree for Sony Xperia SP
dt-bindings: arm: qcom: add Sony Xperia SP
ARM: dts: qcom: msm8960: disable gsbi1 and gsbi5 nodes in msm8960 dtsi
ARM: dts: qcom: msm8960: add gsbi8 and its serial configuration
ARM: dts: qcom: msm8960: add sdcc3 pinctrl states
Link: https://lore.kernel.org/r/20250911220940.3023575-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://github.com/vzapolskiy/linux-lpc32xx into soc/dt
ARM: nxp: lpc: device tree updates for v6.18
This pull request contains device tree changes for ARM NXP LPC32xx and
ARM NXP LPC18xx/LPC43xx for v6.18, please pull the following:
- Frank fixes a multitude of device tree checker warnings reported for
NXP LPC18xx/LPC43xx powered boards,
- Vladimir fixes a number of compile time warnings issued by a dt checker
for NXP LPC32xx powered boards,
- Vladimir replaces Roland as a maintainer of NXP LPC32xx platform
device trees, Roland is inactive for more than 10 years.
* tag 'lpc32xx-dt-for-6.18' of https://github.com/vzapolskiy/linux-lpc32xx:
ARM: dts: lpc32xx: Correct PL080 DMA controller device node name
ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller
ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP
ARM: dts: lpc32xx: Correct SD/MMC controller device node name
ARM: dts: lpc32xx: Correct motor PWM device tree node name
ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms
ARM: dts: lpc18xx: add missed arm,num-irq-priority-bits
ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controller
ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdio
ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]'
ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92
ARM: dts: lpc: add cfg surfix in pinctrl child node
ARM: dts: lpc: add #address-cells and #size-cells for sram node
ARM: dts: lpc18xx: swap clock-names bic and cui
ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0
ARM: dts: lpc18xx: rename node name mmcsd to mmc
ARM: dts: lpc18xx: rename node name flash-controller to spi
Link: https://lore.kernel.org/r/20250911130642.41958-1-vz@mleia.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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A single graph port node without an address (i.e. "reg") should not have
a unit-address, drop it from the "linux,spdif-dit" port node.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250910233923.778992-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Clean-up a couple of clock binding related issues in the the X-Gene DTS.
CPU and I2C nodes aren't clock providers and shouldn't have
"#clock-cells" properties.
A fixed-clock only provides 1 clock, so "#clock-cells" must be 0. The
preferred node name is "clock-<freq>" as well.
The "type" property is undocumented and unused, so drop it.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250910223020.612244-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The slimpro nodes are not MMIO devices, so they don't belong under a
"simple-bus" node. Move them to the top level.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250910214822.508317-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM SoC Device Tree changes for
6.18, please pull the following:
- Taishi-san adds support for the Buffalo WXR-1750DHP using a BCM4708
SoC
* tag 'arm-soc/for-6.18/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: BCM5301X: Add support for Buffalo WXR-1750DHP
dt-bindings: arm: bcm: Add support for Buffalo WXR-1750DHP
Link: https://lore.kernel.org/r/20250910171910.666401-2-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.18, please pull the following:
- Krzysztof fixes a DTC warning for the ARM GIC in bcm2712.dtsi
- Ivan adds the pin controller node(s), an additional GPIO controller,
the second SDHCI controller node for SDIO Wi-Fi, and the UARTA for
Bluetooth to the BCM2712 DTS (Raspberry Pi 5)
- Stanimir adds the Ethernet DT node and enables it for the RP1 sister
chip
- Andrea deletes a number of redundant PCIe DT node enablement, updates
a comment to describe the relationship between bcm2712 and RP1 and
finally enables the USB controllers with RP1
* tag 'arm-soc/for-6.18/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Enable USB devicetree entries for Rpi5
arm64: dts: broadcom: rp1: Add USB nodes
arm64: dts: broadcom: amend the comment about the role of BCM2712 board DTS
arm64: dts: broadcom: delete redundant pcie enablement nodes
arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5
arm64: dts: rp1: Add ethernet DT node
dt-bindings: mmc: Add support for capabilities to Broadcom SDHCI controller
arm64: dts: broadcom: bcm2712: Add UARTA controller node
arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
arm64: dts: broadcom: bcm2712: Add one more GPIO node
arm64: dts: broadcom: bcm2712: Add pin controller nodes
arm64: dts: broadcom: bcm2712: Add default GIC address cells
Link: https://lore.kernel.org/r/20250910171910.666401-3-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
mt7988 (bpi r4):
* enable network
mt7986:
* add dedicated sram node
* add interrupts for RSS to ethernet
mt7981:
* add thermal sensor and auxadc nodes
mt8395 (NIO 12L):
* enable UFS
* add gpio keys to the PMIC
mt8195:
* drop reset for PCIe device
* tag 'v6.17-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
dt-bindings: arm: mediatek: Add grinn,genio-510-sbc
dt-bindings: arm: mediatek: Add grinn,genio-700-sbc
arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds
arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac
arm64: dts: mediatek: mt7988a-bpi-r4: add aliases for ethernet
arm64: dts: mediatek: mt7988: add switch node
arm64: dts: mediatek: mt7988: add basic ethernet-nodes
arm64: dts: mediatek: mt7986: add interrupts for RSS and interrupt names
arm64: dts: mediatek: mt7986: add sram node
arm64: dts: mediatek: add thermal sensor support on mt7981
arm64: dts: mediatek: mt8395-nio-12l: add PMIC and GPIO keys support
arm64: dts: mediatek: mt8395-nio-12l: Enable UFS
arm64: dts: mediatek: mt8183: Fix out of range pull values
arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie0
Link: https://lore.kernel.org/r/46756067-ca2f-4053-b9e9-bc6e66170b21@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM changes for v6.18
1. Drop S3C2416 SoC from bindings, because it was removed from kernel
in 2023.
2. Add Ethernet attached via SROM controller (memory bus) on SMDK5250.
This wasn't tested, but code should work just like it is working on
Exynos5410-based boards.
* tag 'samsung-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: samsung: smdk5250: add sromc node
ARM: dts: samsung: exynos5250: describe sromc bank memory map
ARM: dts: samsung: exynos5410: use multiple tuples for sromc ranges
dt-bindings: arm: samsung: Drop S3C2416
Link: https://lore.kernel.org/r/20250909184559.105777-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Minor improvements in ARM64 DTS for v6.18
Add default address cells for interrupt controllers to fix dtc W=1
warnings on Amazon, APM, Socionext and Toshiba boards.
* tag 'dt64-cleanup-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
arm64: dts: toshiba: tmpv7708: Add default GIC address cells
arm64: dts: amazon: alpine-v3: Add default GIC address cells
arm64: dts: amazon: alpine-v2: Add default GIC address cells
arm64: dts: apm: storm: Add default GIC address cells
arm64: dts: socionext: uniphier-pxs3: Add default PCI interrup controller address cells
arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells
Link: https://lore.kernel.org/r/20250909182256.102840-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux into soc/dt
i2c-gpio-fixes-for-6.18
We have dedictaded bindings for scl/sda nowadays. Switch away from the
deprecated plain 'gpios' property.
* tag 'i2c-gpio-fixes-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
ARM: dts: stm32: use recent scl/sda gpio bindings
ARM: dts: cirrus: ep7211: use recent scl/sda gpio bindings
Link: https://lore.kernel.org/r/aLlgGdrFEjh26knK@shikoro
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Having a platform need a mach-* directory should be seen as a negative,
it means the platform needs special non-standard handling. ARM64 support
does not allow mach-* directories at all. While we may not get to that
given all the non-standard architectures we support, we should still try
to get as close as we can and reduce the number of mach directories.
The mach-hpe/ directory and files, provides just one "feature":
having the kernel print the machine name if the DTB does not also contain
a "model" string (which they always do). To reduce the number of mach-*
directories let's do without that feature and remove this directory.
Note, we drop the l2c_aux_mask = ~0 line, but this is safe as
the fallback GENERIC_DT machine has that as the default.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20250813170308.290349-1-afd@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.18
1. Exynos850 e850 board: Enable Ethernet.
2. Exynos990: Enable watchdog and USB, add more clock controllers.
3. Exynos2200: Switch to 32-bit address space for blocks, because all
peripherals fit there. Add remaining serial engine (USI) nodes
(serial, I2C).
4. New Artpec ARTPEC-8 SoC with board. That's a design from Samsung,
sharing all basic blocks with other Samsung SoCs (busses, clock
controllers, pin controllers, PCIe, USB) and having media/video
related blocks from Axis.
Only basic support is added here: few clock controllers, pin
controller and UART.
5. Several cleanups.
* tag 'samsung-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos990: Enable PERIC0 and PERIC1 clock controllers
arm64: dts: axis: Add ARTPEC-8 Grizzly dts support
arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support
dt-bindings: arm: axis: Add ARTPEC-8 grizzly board
arm64: dts: exynos8895: Minor whitespace cleanup
dt-bindings: arm: Convert Axis board/soc bindings to json-schema
arm64: dts: exynos2200: Add default GIC address cells
arm64: dts: fsd: Add default GIC address cells
arm64: dts: google: gs101: Add default GIC address cells
arm64: dts: exynos5433: Add default GIC address cells
arm64: dts: exynos2200: define all usi nodes
arm64: dts: exynos2200: increase the size of all syscons
arm64: dts: exynos2200: use 32-bit address space for /soc
arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label
arm64: dts: exynos990-r8s: Enable USB
arm64: dts: exynos990-c1s: Enable USB
arm64: dts: exynos990-x1s-common: Enable USB
arm64: dts: exynos990: Add USB nodes
arm64: dts: exynos990: Enable watchdog timer
arm64: dts: exynos: Add Ethernet node for E850-96 board
Link: https://lore.kernel.org/r/20250909180127.99783-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.18
- Add and enable gmac for Agilex5
* tag 'socfpga_dts_updates_for_v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit
arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5
Link: https://lore.kernel.org/r/20250908040718.187857-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
HDMI-CEC and -audio on RK3288-Miqi
* tag 'v6.18-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add HDMI audio to rk3288-miqi
ARM: dts: rockchip: add CEC pinctrl to rk3288-miqi
Link: https://lore.kernel.org/r/12138356.VV5PYv0bhD@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: FriendlyElec NanoPi Zero2, ArmSoM Sige1, Radxa ROCK 2A/2F,
HINLINK H66K / H68K .
Interesting new peripherals: I guess the most interesting one is likely
the NPU on RK3588. The rocket driver has been merged into both the DRM
tree as well as mainline Mesa.
Other stll interesting ones are DW-Displayport on RK3588, DSI on RK3576
(missing soc pwm-support to be useful on most boards), thermal support
and watchdog on RK3576.
The rest peripheral additions on a number of boards (Beelink A1,
Pine{phone,book}, rk3576-evb1-v10, Rock 5*, ...)
* tag 'v6.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (46 commits)
arm64: dts: rockchip: Enable DP2HDMI for ROCK 5 ITX
arm64: dts: rockchip: Enable DisplayPort for rk3588s Cool Pi 4B
arm64: dts: rockchip: Add DP1 for rk3588
arm64: dts: rockchip: Add DP0 for rk3588
arm64: dts: rockchip: Add FriendlyElec NanoPi Zero2
dt-bindings: arm: rockchip: Add FriendlyElec NanoPi Zero2
arm64: dts: rockchip: Add ArmSoM Sige1
dt-bindings: arm: rockchip: Add ArmSoM Sige1
arm64: dts: rockchip: Add Radxa ROCK 2A/2F
dt-bindings: arm: rockchip: Add Radxa ROCK 2A/2F
dt-bindings: soc: rockchip: add missing clock reference for rk3576-dcphy syscon
arm64: dts: rockchip: add USB3 on Beelink A1
arm64: dts: rockchip: add SPDIF audio to Beelink A1
arm64: dts: rockchip: add IR receiver to rk3328-roc
arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro
arm64: dts: rockchip: Further describe the WiFi for the Pinebook Pro
arm64: dts: rockchip: Enable the NPU on NanoPi R6C/R6S
arm64: dts: rockchip: enable NPU on OPI5/5B
arm64: dts: rockchip: Add Bluetooth on rk3576-evb1-v10
arm64: dts: rockchip: Add WiFi on rk3576-evb1-v10
...
Link: https://lore.kernel.org/r/5241735.C4sosBPzcN@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
T-HEAD Devicetrees for v6.18
Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD
TH1520 SoC used by the Lichee Pi 4A board. This node enables support for
the GPU using the drm/imagination driver.
By adding this node, the kernel can recognize and initialize the GPU,
providing graphics acceleration capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC. The display controller and HDMI
output are still a work in progress.
Also included is a MAINTAINERS patch that adds an entry for the T-Head
SoC patchwork.
Signed-off-by: Drew Fustini <fustini@kernel.org>
* tag 'thead-dt-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux:
MAINTAINERS: Add RISC-V T-HEAD SoC patchwork
riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node
Link: https://lore.kernel.org/r/aLyIXR1G9DUzwGWc@x1
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- Enable Netfilter legacy tables support,
- Drop CONFIG_IP_NF_FILTER=m, CONFIG_IP_NF_MANGLE=m,
CONFIG_IP6_NF_FILTER=m, and CONFIG_IP6_NF_MANGLE=m (auto-modular
since commit 9fce66583f06c212 ("netfilter: Exclude LEGACY TABLES on
PREEMPT_RT.")),
- Enable legacy EBTABLES support (no longer auto-selected since commit
9fce66583f06c212 ("netfilter: Exclude LEGACY TABLES on
PREEMPT_RT.")),
- Drop CONFIG_CDROM_PKTCDVD=m (removed in commit 1cea5180f2f812c4
("block: remove pktcdvd driver")),
- Move CONFIG_CRC_BENCHMARK=y (moved in commit 89a51591405e09a8
("lib/crc: Move files into lib/crc/")).
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Link: https://patch.msgid.link/012bc96a01eef989b39eedbe84591bd50c022e57.1754904412.git.geert@linux-m68k.org
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The function signatures of the m68k-optimized implementations of the
find_{first,next}_{,zero_}bit() helpers do not match the generic
variants.
Fix this by changing all non-pointer inputs and outputs to "unsigned
long", and updating a few local variables.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202509092305.ncd9mzaZ-lkp@intel.com/
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: "Yury Norov (NVIDIA)" <yury.norov@gmail.com>
Link: https://patch.msgid.link/de6919554fbb4cd1427155c6bafbac8a9df822c8.1757517135.git.geert@linux-m68k.org
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Detect the Bhyve hypervisor and enable 15-bit MSI support if available.
Detecting Bhyve used to be a purely cosmetic issue of the kernel printing
'Hypervisor detected: Bhyve' at boot time.
But FreeBSD 15.0 will support¹ the 15-bit MSI enlightenment to support
more than 255 vCPUs (http://david.woodhou.se/ExtDestId.pdf) which means
there's now actually some functional reason to do so.
¹ https://github.com/freebsd/freebsd-src/commit/313a68ea20b4
[ bp: Massage, move tail comment ontop. ]
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://lore.kernel.org/03802f6f7f5b5cf8c5e8adfe123c397ca8e21093.camel@infradead.org
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|
Map the hyp text section as RO, there are no secrets there
and that allows the kernel extract info for debugging.
As in case of panic we can now dump the faulting instructions
similar to the kernel.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
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|
Similar to the kernel panic, where the instruction code is printed,
we can do the same for hypervisor panics.
This patch does that only in case of “CONFIG_NVHE_EL2_DEBUG” or nvhe.
The next patch adds support for pKVM.
Also, remove the hardcoded argument dump_kernel_instr().
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Kunwu Chan <chentao@kylinos.cn>
Reviewed-by: Kunwu Chan <chentao@kylinos.cn>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
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Currently uprobe syscall handles all errors with forcing SIGILL to current
process. As suggested by Andrii it'd be helpful for uprobe syscall detection
to return error value for the !in_uprobe_trampoline check.
This way we could just call uprobe syscall and based on return value we will
find out if the kernel has it.
Suggested-by: Andrii Nakryiko <andrii@kernel.org>
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Andrii Nakryiko <andrii@kernel.org>
Acked-by: Oleg Nesterov <oleg@redhat.com>
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The ns_bpf_qdisc selftest triggers a kernel panic:
Unable to handle kernel paging request at virtual address ffffffffa38dbf58
Current test_progs pgtable: 4K pagesize, 57-bit VAs, pgdp=0x00000001109cc000
[ffffffffa38dbf58] pgd=000000011fffd801, p4d=000000011fffd401, pud=000000011fffd001, pmd=0000000000000000
Oops [#1]
Modules linked in: bpf_testmod(OE) xt_conntrack nls_iso8859_1 [...] [last unloaded: bpf_testmod(OE)]
CPU: 1 UID: 0 PID: 23584 Comm: test_progs Tainted: G W OE 6.17.0-rc1-g2465bb83e0b4 #1 NONE
Tainted: [W]=WARN, [O]=OOT_MODULE, [E]=UNSIGNED_MODULE
Hardware name: Unknown Unknown Product/Unknown Product, BIOS 2024.01+dfsg-1ubuntu5.1 01/01/2024
epc : __qdisc_run+0x82/0x6f0
ra : __qdisc_run+0x6e/0x6f0
epc : ffffffff80bd5c7a ra : ffffffff80bd5c66 sp : ff2000000eecb550
gp : ffffffff82472098 tp : ff60000096895940 t0 : ffffffff8001f180
t1 : ffffffff801e1664 t2 : 0000000000000000 s0 : ff2000000eecb5d0
s1 : ff60000093a6a600 a0 : ffffffffa38dbee8 a1 : 0000000000000001
a2 : ff2000000eecb510 a3 : 0000000000000001 a4 : 0000000000000000
a5 : 0000000000000010 a6 : 0000000000000000 a7 : 0000000000735049
s2 : ffffffffa38dbee8 s3 : 0000000000000040 s4 : ff6000008bcda000
s5 : 0000000000000008 s6 : ff60000093a6a680 s7 : ff60000093a6a6f0
s8 : ff60000093a6a6ac s9 : ff60000093140000 s10: 0000000000000000
s11: ff2000000eecb9d0 t3 : 0000000000000000 t4 : 0000000000ff0000
t5 : 0000000000000000 t6 : ff60000093a6a8b6
status: 0000000200000120 badaddr: ffffffffa38dbf58 cause: 000000000000000d
[<ffffffff80bd5c7a>] __qdisc_run+0x82/0x6f0
[<ffffffff80b6fe58>] __dev_queue_xmit+0x4c0/0x1128
[<ffffffff80b80ae0>] neigh_resolve_output+0xd0/0x170
[<ffffffff80d2daf6>] ip6_finish_output2+0x226/0x6c8
[<ffffffff80d31254>] ip6_finish_output+0x10c/0x2a0
[<ffffffff80d31446>] ip6_output+0x5e/0x178
[<ffffffff80d2e232>] ip6_xmit+0x29a/0x608
[<ffffffff80d6f4c6>] inet6_csk_xmit+0xe6/0x140
[<ffffffff80c985e4>] __tcp_transmit_skb+0x45c/0xaa8
[<ffffffff80c995fe>] tcp_connect+0x9ce/0xd10
[<ffffffff80d66524>] tcp_v6_connect+0x4ac/0x5e8
[<ffffffff80cc19b8>] __inet_stream_connect+0xd8/0x318
[<ffffffff80cc1c36>] inet_stream_connect+0x3e/0x68
[<ffffffff80b42b20>] __sys_connect_file+0x50/0x88
[<ffffffff80b42bee>] __sys_connect+0x96/0xc8
[<ffffffff80b42c40>] __riscv_sys_connect+0x20/0x30
[<ffffffff80e5bcae>] do_trap_ecall_u+0x256/0x378
[<ffffffff80e69af2>] handle_exception+0x14a/0x156
Code: 892a 0363 1205 489c 8bc1 c7e5 2d03 084a 2703 080a (2783) 0709
---[ end trace 0000000000000000 ]---
The bpf_fifo_dequeue prog returns a skb which is a pointer. The pointer
is treated as a 32bit value and sign extend to 64bit in epilogue. This
behavior is right for most bpf prog types but wrong for struct ops which
requires RISC-V ABI.
So let's sign extend struct ops return values according to the function
model and RISC-V ABI([0]).
[0]: https://riscv.org/wp-content/uploads/2024/12/riscv-calling.pdf
Fixes: 25ad10658dc1 ("riscv, bpf: Adapt bpf trampoline to optimized riscv ftrace framework")
Signed-off-by: Hengqi Chen <hengqi.chen@gmail.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Tested-by: Pu Lehui <pulehui@huawei.com>
Reviewed-by: Pu Lehui <pulehui@huawei.com>
Link: https://lore.kernel.org/bpf/20250908012448.1695-1-hengqi.chen@gmail.com
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The bpf_flush_icache() is done by bpf_arch_text_copy() already.
Remove the duplicated one in arch_prepare_bpf_trampoline().
Signed-off-by: Hengqi Chen <hengqi.chen@gmail.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Reviewed-by: Pu Lehui <pulehui@huawei.com>
Link: https://lore.kernel.org/bpf/20250904105119.21861-1-hengqi.chen@gmail.com
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The logic for allocating ppc64_stub_entry trampolines in the .stubs
section relies on an inline sentinel, where a NULL .funcdata member
indicates an available slot.
While preceding commits fixed the initialization bugs that led to ftrace
stub corruption, the sentinel-based approach remains fragile: it depends
on an implicit convention between subsystems modifying different
struct types in the same memory area.
Replace the sentinel with an explicit counter, module->arch.num_stubs.
Instead of iterating through memory to find a NULL marker, the module
loader uses this counter as the boundary for the next free slot.
This simplifies the allocation code, hardens it against future changes
to stub structures, and removes the need for an extra relocation slot
previously reserved to terminate the sentinel search.
Signed-off-by: Joe Lawrence <joe.lawrence@redhat.com>
Acked-by: Naveen N Rao (AMD) <naveen@kernel.org>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/20250912142740.3581368-4-joe.lawrence@redhat.com
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CONFIG_PPC_FTRACE_OUT_OF_LINE introduced setup_ftrace_ool_stubs() to
extend the ppc64le module .stubs section with an array of
ftrace_ool_stub structures for each patchable function.
Fix its ppc64_stub_entry stub reservation loop to properly write across
all of the num_stubs used and not just the first entry.
Fixes: eec37961a56a ("powerpc64/ftrace: Move ftrace sequence out of line")
Signed-off-by: Joe Lawrence <joe.lawrence@redhat.com>
Acked-by: Naveen N Rao (AMD) <naveen@kernel.org>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/20250912142740.3581368-3-joe.lawrence@redhat.com
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When an ftrace call site is converted to a NOP, its corresponding
dyn_ftrace record should have its ftrace_ops pointer set to
ftrace_nop_ops.
Correct the powerpc implementation to ensure the
ftrace_rec_set_nop_ops() helper is called on all successful NOP
initialization paths. This ensures all ftrace records are consistent
before being handled by the ftrace core.
Fixes: eec37961a56a ("powerpc64/ftrace: Move ftrace sequence out of line")
Suggested-by: Naveen N Rao <naveen@kernel.org>
Signed-off-by: Joe Lawrence <joe.lawrence@redhat.com>
Acked-by: Naveen N Rao (AMD) <naveen@kernel.org>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/20250912142740.3581368-2-joe.lawrence@redhat.com
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Configure mbm_event mode on AMD platforms. On AMD platforms, it is
recommended to use the mbm_event mode, if supported, to prevent the
hardware from resetting counters between reads. This can result in
misleading values or display "Unavailable" if no counter is assigned
to the event.
Enable mbm_event mode, known as ABMC (Assignable Bandwidth Monitoring
Counters) on AMD, by default if the system supports it.
Update ABMC across all logical processors within the resctrl domain to
ensure proper functionality.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
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When Linux is booted at EL1, host_data_ptr() resolves to the nVHE
hypervisor's copy of host data. When hyp mode isn't available for
KVM the nVHE percpu bases remain uninitialized. Consequently, any usage
of host_data_ptr() will result in a NULL dereference which has been
observed in KVM's trace filtering helpers.
Add an early return to the trace filtering helpers if KVM isn't
initialized, avoiding the NULL dereference. Take this opportunity
to move the TRBE-skipping checks to a common helper.
Fixes: 054b88391bbe2 ("KVM: arm64: Support trace filtering for guests")
Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
Reviewed-by: James Clark <james.clark@linaro.org>
[maz: repainted the helpers to be readable, and the commit message
with Oliver's suggestion]
Signed-off-by: Marc Zyngier <maz@kernel.org>
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System software reads resctrl event data for a particular resource by writing
the RMID and Event Identifier (EvtID) to the QM_EVTSEL register and then
reading the event data from the QM_CTR register.
In ABMC mode, the event data of a specific counter ID is read by setting the
following fields: QM_EVTSEL.ExtendedEvtID = 1, QM_EVTSEL.EvtID = L3CacheABMC
(=1) and setting QM_EVTSEL.RMID to the desired counter ID. Reading the QM_CTR
then returns the contents of the specified counter ID. RMID_VAL_ERROR bit is
set if the counter configuration is invalid, or if an invalid counter ID is
set in the QM_EVTSEL.RMID field. RMID_VAL_UNAVAIL bit is set if the counter
data is unavailable.
Introduce resctrl_arch_reset_cntr() and resctrl_arch_cntr_read() to reset and
read event data for a specific counter.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
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resctrl_arch_rmid_read() adjusts the value obtained from MSR_IA32_QM_CTR to
account for the overflow for MBM events and apply counter scaling for all the
events. This logic is common to both reading an RMID and reading a hardware
counter directly.
Refactor the hardware value adjustment logic into get_corrected_val() to
prepare for support of reading a hardware counter.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
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with ABMC
The ABMC feature allows users to assign a hardware counter to an RMID,
event pair and monitor bandwidth usage as long as it is assigned. The
hardware continues to track the assigned counter until it is explicitly
unassigned by the user.
Implement an x86 architecture-specific handler to configure a counter. This
architecture specific handler is called by resctrl fs when a counter is
assigned or unassigned as well as when an already assigned counter's
configuration should be updated. Configure counters by writing to the
L3_QOS_ABMC_CFG MSR, specifying the counter ID, bandwidth source (RMID),
and event configuration.
The ABMC feature details are documented in APM [1] available from [2].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth
Monitoring (ABMC).
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
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The ABMC feature allows users to assign a hardware counter to an RMID,
event pair and monitor bandwidth usage as long as it is assigned. The
hardware continues to track the assigned counter until it is explicitly
unassigned by the user.
The ABMC feature implements an MSR L3_QOS_ABMC_CFG (C000_03FDh).
ABMC counter assignment is done by setting the counter id, bandwidth
source (RMID) and bandwidth configuration.
Attempts to read or write the MSR when ABMC is not enabled will result
in a #GP(0) exception.
Introduce the data structures and definitions for MSR L3_QOS_ABMC_CFG
(0xC000_03FDh):
=========================================================================
Bits Mnemonic Description Access Reset
Type Value
=========================================================================
63 CfgEn Configuration Enable R/W 0
62 CtrEn Enable/disable counting R/W 0
61:53 – Reserved MBZ 0
52:48 CtrID Counter Identifier R/W 0
47 IsCOS BwSrc field is a CLOSID R/W 0
(not an RMID)
46:44 – Reserved MBZ 0
43:32 BwSrc Bandwidth Source R/W 0
(RMID or CLOSID)
31:0 BwType Bandwidth configuration R/W 0
tracked by the CtrID
==========================================================================
The ABMC feature details are documented in APM [1] available from [2].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth
Monitoring (ABMC).
[ bp: Touchups. ]
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
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Add the functionality to enable/disable the AMD ABMC feature.
The AMD ABMC feature is enabled by setting enabled bit(0) in the
L3_QOS_EXT_CFG MSR. When the state of ABMC is changed, the MSR needs to be
updated on all the logical processors in the QOS Domain.
Hardware counters will reset when ABMC state is changed.
[ bp: Massage commit message. ]
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
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ABMC feature details are reported via CPUID Fn8000_0020_EBX_x5.
Bits Description
15:0 MAX_ABMC Maximum Supported Assignable Bandwidth
Monitoring Counter ID + 1
The ABMC feature details are documented in APM [1] available from [2].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth
Monitoring (ABMC).
Detect the feature and number of assignable counters supported. For backward
compatibility, upon detecting the assignable counter feature, enable the
mbm_total_bytes and mbm_local_bytes events that users are familiar with as
part of original L3 MBM support.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
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The cache allocation and memory bandwidth allocation feature properties are
consolidated into struct resctrl_cache and struct resctrl_membw respectively.
In preparation for more monitoring properties that will clobber the existing
resource struct more, re-organize the monitoring specific properties to also
be in a separate structure.
Also convert "bandwidth sources" terminology to "memory transactions" to have
consistency within resctrl for related monitoring features.
[ bp: Massage commit message. ]
Suggested-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
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Add a kernel command-line parameter to enable or disable the exposure of
the ABMC (Assignable Bandwidth Monitoring Counters) hardware feature to
resctrl.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
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Users can create as many monitor groups as RMIDs supported by the hardware.
However, the bandwidth monitoring feature on AMD only guarantees that RMIDs
currently assigned to a processor will be tracked by hardware. The counters of
any other RMIDs which are no longer being tracked will be reset to zero.
The MBM event counters return "Unavailable" for the RMIDs that are not tracked
by hardware. So, there can be only limited number of groups that can give
guaranteed monitoring numbers. With ever changing configurations there is no
way to definitely know which of these groups are being tracked during
a particular time. Users do not have the option to monitor a group or set of
groups for a certain period of time without worrying about RMID being reset in
between.
The ABMC feature allows users to assign a hardware counter to an RMID, event
pair and monitor bandwidth usage as long as it is assigned. The hardware
continues to track the assigned counter until it is explicitly unassigned by
the user. There is no need to worry about counters being reset during this
period. Additionally, the user can specify the type of memory transactions
(e.g., reads, writes) for the counter to track.
Without ABMC enabled, monitoring will work in current mode without assignment
option.
The Linux resctrl subsystem provides an interface that allows monitoring of up
to two memory bandwidth events per group, selected from a combination of
available total and local events. When ABMC is enabled, two events will be
assigned to each group by default, in line with the current interface design.
Users will also have the option to configure which types of memory
transactions are counted by these events.
Due to the limited number of available counters (32), users may quickly
exhaust the available counters. If the system runs out of assignable ABMC
counters, the kernel will report an error. In such cases, users will need to
unassign one or more active counters to free up counters for new assignments.
resctrl will provide options to assign or unassign events through the
group-specific interface file.
The feature is detected via CPUID_Fn80000020_EBX_x00 bit 5: ABMC (Assignable
Bandwidth Monitoring Counters).
The ABMC feature details are documented in APM [1] available from [2]. [1]
AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth
Monitoring (ABMC).
[ bp: Massage commit message, fixup enumeration due to VMSCAPE ]
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
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There's a rule in computer programming that objects appear zero, once, or many
times. So code accordingly.
There are two MBM events and resctrl is coded with a lot of
if (local)
do one thing
if (total)
do a different thing
Change the rdt_mon_domain and rdt_hw_mon_domain structures to hold arrays of
pointers to per event data instead of explicit fields for total and local
bandwidth.
Simplify by coding for many events using loops on which are enabled.
Move resctrl_is_mbm_event() to <linux/resctrl.h> so it can be used more
widely. Also provide a for_each_mbm_event_id() helper macro.
Cleanup variable names in functions touched to consistently use "eventid" for
those with type enum resctrl_event_id.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
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rdt_mon_features is used as a bitmask of enabled monitor events. A monitor
event's status is now maintained in mon_evt::enabled with all monitor events'
mon_evt structures found in the filesystem's mon_event_all[] array.
Remove the remaining uses of rdt_mon_features.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
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This ensures that, if a VCPU has "observed" that an IO registration has
occurred, the instruction currently being trapped or emulated will also
observe the IO registration.
At the same time, enforce that kvm_get_bus() is used only on the
update side, ensuring that a long-term reference cannot be obtained by
an SRCU reader.
Signed-off-by: Keir Fraser <keirf@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
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In preparation to remove synchronize_srcu() from MMIO registration,
remove the distributor's dependency on this implicit barrier by
direct acquire-release synchronization on the flag write and its
lock-free check.
Signed-off-by: Keir Fraser <keirf@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
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