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2025-09-16RISC-V: KVM: Write hgatp register with valid mode bitsFangyu Yu1-1/+2
According to the RISC-V Privileged Architecture Spec, when MODE=Bare is selected,software must write zero to the remaining fields of hgatp. We have detected the valid mode supported by the HW before, So using a valid mode to detect how many vmid bits are supported. Fixes: fd7bb4a251df ("RISC-V: KVM: Implement VMID allocator") Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Reviewed-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Link: https://lore.kernel.org/r/20250821142542.2472079-2-guoren@kernel.org Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16RISC-V: KVM: Allow bfloat16 extension for Guest/VMQuan Zhou2-0/+9
Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zfbfmin/Zvfbfmin/Zvfbfwma extension for Guest/VM. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/f846cecd330ab9fc88211c55bc73126f903f8713.1754646071.git.zhouquan@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16RISC-V: KVM: Allow Zicbop extension for Guest/VMQuan Zhou2-0/+3
Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zicbop extension for Guest/VM. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/db4a9b679cc653bb6f5f5574e4196de7a980e458.1754646071.git.zhouquan@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16RISC-V: KVM: Provide UAPI for Zicbop block sizeQuan Zhou2-0/+15
We're about to allow guests to use the Zicbop extension. KVM userspace needs to know the cache block size in order to properly advertise it to the guest. Provide a virtual config register for userspace to get it with the GET_ONE_REG API, but setting it cannot be supported, so disallow SET_ONE_REG. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/befd8403cd76d7adb97231ac993eaeb86bf2582c.1754646071.git.zhouquan@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16RISC-V: KVM: Change zicbom/zicboz block size to depend on the host isaQuan Zhou1-6/+6
The zicbom/zicboz block size registers should depend on the host's isa, the reason is that we otherwise create an ioctl order dependency on the VMM. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviwed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Link: https://lore.kernel.org/r/fef5907425455ecd41b224e0093f1b6bc4067138.1754646071.git.zhouquan@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16RISC-V: KVM: Add support for SBI_FWFT_POINTER_MASKING_PMLENSamuel Holland3-1/+94
Pointer masking is controlled through a WARL field in henvcfg. Expose the feature only if at least one PMLEN value is supported for VS-mode. Allow the VMM to block access to the feature by disabling the Smnpm ISA extension in the guest. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20250111004702.2813013-3-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16alpha: unobfuscate _PAGE_P() definitionAl Viro1-1/+1
Way, way back it used to be _PAGE_NORMAL((x) | ((x & _PAGE_FOW) ? 0 : _PAGE_FOW | _PAGE_COW)) Then (in 1.3.54) _PAGE_COW had died. Result: _PAGE_NORMAL((x) | ((x & _PAGE_FOW) ? 0 : _PAGE_FOW)) which is somewhat... obscure. What it does is simply _PAGE_NORMAL((x) | _PAGE_FOW) and IMO that's easier to follow. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2025-09-16kill FIRST_USER_PGD_NRAl Viro2-2/+0
dead since 2005, time to bury the body... Reviewed-by: Michal Simek <michal.simek@amd.com> # microblaze Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2025-09-16ARM: OMAP2+: clock: convert from round_rate() to determine_rate()Brian Masney1-5/+7
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. The change to virt_prcm_set_ops had to be made manually. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/20250710-arm32-clk-round-rate-v1-2-a9146b77aca9@redhat.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-09-16ARM: OMAP1: clock: convert from round_rate() to determine_rate()Brian Masney1-6/+13
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <bmasney@redhat.com> Acked-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20250710-arm32-clk-round-rate-v1-1-a9146b77aca9@redhat.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-09-15Merge tag 'stm32-dt-for-v6.18-1' of ↵Arnd Bergmann23-39/+493
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.18, round 1 Highlights: ---------- - MPU: - STM32MP13: - Add missing Ethernet1/2 PTP reference clocks. - Add Hardware debug port (HDP). - STMP32MP15: - Add resets property to m_can nodes. - Add Hardware debug port (HDP) and enable it on stm32mp157c-dk2 board. - Reserve leds for CM4 on stm32mp15xx-ed1 and stm32mp15xx-dkx. - stm32mp151c-plyaqm: Use correct dai-format property. - STM32MP23: - Add Ethernet1 MAC controller on stm32mp235f-dk board: It is connected to a RTL8211F-CG phy through RGMII. - Fix GPIO bank definition & memory size (DDR). - STM32MP25: - Add Ethernet1 MAC controller on stm32mp257f-dk board. It is connected to a RTL8211F-CG phy through RGMII. - Add Ethernet1 MAC controller on stm32mp257f-ev1 board. It is connected to a RTL8211F-CG phy through RGMII. - Add display support by enabling the following IPs on stm32mp257f-ev1: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel LVDS backlight as GPIO backlight * ILI2511 i2c touchscreen - Add PCIe Root complex and Endpoint support on stm32mp257f-ev1. Root complex mode is used by default. * tag 'stm32-dt-for-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (30 commits) arm64: dts: st: fix memory region size on stm32mp235f-dk arm64: dts: st: remove gpioj and gpiok banks from stm32mp231 arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1 arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk arm64: dts: st: add eth1 pins for stm32mp2x platforms ARM: dts: stm32: add missing PTP reference clocks on stm32mp13x SoCs arm64: dts: st: enable display support on stm32mp257f-ev1 board arm64: dts: st: add clock-cells to syscfg node on stm32mp251 arm64: dts: st: add lvds support on stm32mp255 arm64: dts: st: add ltdc support on stm32mp255 arm64: dts: st: add ltdc support on stm32mp251 ARM: dts: stm32: add resets property to m_can nodes in the stm32mp153 dt-binding: can: m_can: add optional resets property arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board arm64: dts: st: Add PCIe Endpoint mode on stm32mp251 arm64: dts: st: Add PCIe Root Complex mode on stm32mp251 arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi arm64: defconfig: Enable STMicroelectronics STM32 DMA3 support ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp157c-dk2 board ... Link: https://lore.kernel.org/r/13153fc2-1abe-4d53-807a-5d289981a63d@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15x86/bugs: Remove uses of cpu_mitigations_off()David Kaplan1-5/+5
cpu_mitigations_off() is no longer needed because all bugs use attack vector controls to select a mitigation, and cpu_mitigations_off() is equivalent to no attack vectors being selected. Remove the few remaining unnecessary uses of this function in this file. Signed-off-by: David Kaplan <david.kaplan@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
2025-09-15KVM: SEV: Add SEV-SNP CipherTextHiding supportAshish Kalra1-1/+31
Ciphertext hiding prevents host accesses from reading the ciphertext of SNP guest private memory. Instead of reading ciphertext, the host reads will see constant default values (0xff). The SEV ASID space is split into SEV and SEV-ES/SEV-SNP ASID ranges. Enabling ciphertext hiding further splits the SEV-ES/SEV-SNP ASID space into separate ASID ranges for SEV-ES and SEV-SNP guests. Add a new off-by-default kvm-amd module parameter to enable ciphertext hiding and allow the admin to configure the SEV-ES and SEV-SNP ASID ranges. Simply cap the maximum SEV-SNP ASID as appropriate, i.e. don't reject loading KVM or disable ciphertest hiding for a too-big value, as KVM's general approach for module params is to sanitize inputs based on hardware/kernel support, not burn the world down. This also allows the admin to use -1u to assign all SEV-ES/SNP ASIDs to SNP without needing dedicated handling in KVM. Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Ashish Kalra <ashish.kalra@amd.com> Co-developed-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/95abc49edfde36d4fb791570ea2a4be6ad95fd0d.1755721927.git.ashish.kalra@amd.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-09-15KVM: SEV: Introduce new min,max sev_es and sev_snp asid variablesAshish Kalra1-9/+27
Introduce new min, max sev_es_asid and sev_snp_asid variables. The new {min,max}_{sev_es,snp}_asid variables along with existing {min,max}_sev_asid variable simplifies partitioning of the SEV and SEV-ES+ ASID space. Suggested-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Ashish Kalra <ashish.kalra@amd.com> Link: https://lore.kernel.org/r/1db48277e8e96a633d734786ea69bf830f014857.1755721927.git.ashish.kalra@amd.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-09-15KVM: arm64: Update stale comment for sanitise_mte_tags()Alexandru Elisei1-5/+2
Commit c911f0d46879 ("KVM: arm64: permit all VM_MTE_ALLOWED mappings with MTE enabled") allowed VM_SHARED VMAs in a VM with MTE enabled, so remove the comment to the contrary. Commit d77e59a8fccd ("arm64: mte: Lock a page for MTE tag initialisation") removed the race that can lead to tags being zeroed more than once when multiple threads attempt initialisation at the same time, so remove the comment about mmap_lock too. Note that sanitise_mte_tags() was never called with the mmap_lock held from user_mem_abort() and the race was prevented by kvm->mmu_lock. However, the function still requires to have the kvm->mmu_lock held to ensure that the memory remains mapped in the userspace process while the tags are zeroed. Document this in a comment. CC: Peter Collingbourne <pcc@google.com> CC: Catalin Marinas <catalin.marinas@arm.com> CC: Steven Price <steven.price@arm.com> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-09-15x86/sev: Guard sev_evict_cache() with CONFIG_AMD_MEM_ENCRYPTTom Lendacky1-19/+19
The sev_evict_cache() is guest-related code and should be guarded by CONFIG_AMD_MEM_ENCRYPT, not CONFIG_KVM_AMD_SEV. CONFIG_AMD_MEM_ENCRYPT=y is required for a guest to run properly as an SEV-SNP guest, but a guest kernel built with CONFIG_KVM_AMD_SEV=n would get the stub function of sev_evict_cache() instead of the version that performs the actual eviction. Move the function declarations under the appropriate #ifdef. Fixes: 7b306dfa326f ("x86/sev: Evict cache lines during SNP memory validation") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: stable@kernel.org # 6.16.x Link: https://lore.kernel.org/r/70e38f2c4a549063de54052c9f64929705313526.1757708959.git.thomas.lendacky@amd.com
2025-09-15x86/bugs: Simplify SSB cmdline parsingDavid Kaplan2-80/+41
Simplify the SSB command line parsing by selecting a mitigation directly, as is done in most of the simpler vulnerabilities. Use early_param() instead of cmdline_find_option() for consistency with the other mitigation selections. Signed-off-by: David Kaplan <david.kaplan@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Link: https://lore.kernel.org/r/20250819192200.2003074-4-david.kaplan@amd.com
2025-09-15arm64: dts: st: fix memory region size on stm32mp235f-dkAmelie Delaunay1-1/+1
STM32MP23x SoCs provide a DDR controller supporting up to 4GB/16-bit. The control pin to properly configure 4GB/16-bit is not routed on stm32mp235f-dk, that's why the board only supports 2GB. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250910-stm32mp231_gpio_update-v2-2-8510efa2c5cf@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: remove gpioj and gpiok banks from stm32mp231Amelie Delaunay1-22/+0
STM32MP23x supports AJ, AK and AL packages, where PI12 to PI15, PJ0 to PJ15 (whole J bank) and PK0 to PK7 (whole K bank) pins are not available. It means gpioj and gpiok nodes are useless in stm32mp231. Remove them. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250910-stm32mp231_gpio_update-v2-1-8510efa2c5cf@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: enable ethernet1 controller on stm32mp235f-dkGatien Chevallier1-0/+23
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp235f-dk board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-4-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1Gatien Chevallier1-0/+24
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. It can either be used as a standalone Ethernet controller or be connected to the internal TSN capable switch. For this board, keep the standalone setup. Also enable this peripheral on the stm32mp257f-ev1 board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-3-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: enable ethernet1 controller on stm32mp257f-dkGatien Chevallier1-0/+23
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp257f-dk board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-2-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add eth1 pins for stm32mp2x platformsGatien Chevallier1-0/+126
Eth1 ethernet controller is present on every stm32mp2x vendor boards. Describe the pinctrl of eth1 for each of them. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-1-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15ARM: dts: stm32: add missing PTP reference clocks on stm32mp13x SoCsGatien Chevallier2-0/+4
ETH1/2 miss their PTP reference clock in the SoC device tree. Add them as the fallback is not correctly handled for PPS generation and it seems there's no reason to not add them. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250901-relative_flex_pps-v4-3-b874971dfe85@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: enable display support on stm32mp257f-ev1 boardRaphael Gallais-Pou1-0/+76
Enable the following IPs on stm32mp257f-ev1 in order to get display: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel LVDS backlight as GPIO backlight * ILI2511 i2c touchscreen Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-13-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add clock-cells to syscfg node on stm32mp251Raphael Gallais-Pou1-0/+1
Make the syscfg node a clock provider so clock consumers can reach child clocks through device-tree. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-12-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add lvds support on stm32mp255Raphael Gallais-Pou1-0/+12
The LVDS is used on STM32MP2 as a display interface. Add the LVDS node. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-11-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add ltdc support on stm32mp255Raphael Gallais-Pou2-0/+12
Add the LTDC node for stm32mp255 SoC and handle its loopback clocks. ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is semantically correct, it for now leads to an improper setting of the clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does not support changing rates yet. To overcome this issue, a fixed clock can be used for the kernel clock. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-10-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add ltdc support on stm32mp251Raphael Gallais-Pou1-0/+12
The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display interfaces. Add the LTDC node. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-9-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15ARM: dts: stm32: add resets property to m_can nodes in the stm32mp153Marc Kleine-Budde1-0/+2
On the STM32MP153 the m_cam IP cores (a.k.a. FDCAN) have an external shared reset in the RCC. Add the reset to both m_can nodes. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20250807-stm32mp15-m_can-add-reset-v2-2-f69ebbfced1f@pengutronix.de Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 boardChristian Bruel1-0/+21
Add PCIe RC and EP support on stm32mp257f-ev1 board. Default to RC mode. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250820075411.1178729-12-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: Add PCIe Endpoint mode on stm32mp251Christian Bruel1-0/+15
Add pcie_ep node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Endpoint mode Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20250820075411.1178729-11-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: Add PCIe Root Complex mode on stm32mp251Christian Bruel1-0/+44
Add pcie_rc node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Root Complex mode Supports Gen1/Gen2, single lane, MSI interrupts using the ARM GICv2m Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20250820075411.1178729-10-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsiChristian Bruel1-0/+20
Add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi init: forces GPIO to low while probing so CLKREQ is low for phy_init default: restore the AFMUX after controller probe Add Analog pins of PCIe to perform power cycle Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250820075411.1178729-9-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: defconfig: Enable STMicroelectronics STM32 DMA3 supportPatrice Chotard1-0/+1
Enable STMicroelectronics STM32 DMA3 support as module. STM32 DMA3 is used among others by STM32 Octo SPI driver on STM32MP257F-EV1 board. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250821-upstream_defconfig_enable_stm32_dma3-v1-1-d9c1b71883d9@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp157c-dk2 boardClément Le Goffic1-0/+6
On the stm32mp157fc-dk2 board, we can observe the hdp GPOVAL function on SoC pin E13 accessible on the pin 5 on the Arduino connector CN13. Add the relevant configuration but keep it disabled as it's used for debug only. Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-8-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15ARM: dts: stm32: add alternate pinmux for HDP pin and add HDP pinctrl nodeClément Le Goffic1-0/+25
Introduce hdp node to output a user defined value on port hdp2. Add pinctrl nodes to be able to output this signal on one SoC pin. Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-7-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add Hardware debug port (HDP) on stm32mp25Clément Le Goffic1-0/+7
Add the hdp devicetree node for stm32mp25 SoC family Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-6-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15xtensa: use HZ_PER_MHZ in platform_calibrate_ccountThorsten Blum1-2/+3
Replace the hardcoded 1000000UL with the HZ_PER_MHZ unit macro, and add a space in "10 MHz" to improve the readability of the error message. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Message-Id: <20250915120540.2150841-3-thorsten.blum@linux.dev> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2025-09-15x86/bugs: Use early_param() for spectre_v2David Kaplan1-99/+82
Most of the mitigations in bugs.c use early_param() for command line parsing. Rework the spectre_v2 and nospectre_v2 command line options to be consistent with the others. Remove spec_v2_print_cond() as informing the user of the their cmdline choice isn't interesting. [ bp: Zap spectre_v2_check_cmd(). ] Signed-off-by: David Kaplan <david.kaplan@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Link: https://lore.kernel.org/r/20250819192200.2003074-3-david.kaplan@amd.com
2025-09-15x86/bugs: Use early_param() for spectre_v2_userDavid Kaplan1-42/+26
Most of the mitigations in bugs.c use early_param() to parse their command line options. Modify spectre_v2_user to use early_param() for consistency. Remove spec_v2_user_print_cond() because informing a user about their cmdline choice isn't very interesting and the chosen mitigation is already printed in spectre_v2_user_update_mitigation(). Signed-off-by: David Kaplan <david.kaplan@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Link: https://lore.kernel.org/r/20250819192200.2003074-2-david.kaplan@amd.com
2025-09-15ARM: dts: socionext: Drop "linux,spdif-dit" port node unit-addressRob Herring (Arm)1-2/+2
A single graph port node without an address (i.e. "reg") should not have a unit-address, drop it from the "linux,spdif-dit" port node. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250910233740.777077-2-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'imx-dt64-6.18' of ↵Arnd Bergmann83-1485/+9431
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt i.MX arm64 device tree changes for 6.18: - New device trees: TQMa91xx/MBa91xxCA, Ultratronik Ultra-MACH SBC, SolidRun i.MX8MP SoM, i.MX8ULP EVK9, TQMLS1012AL, i.MX91 11x11 EVK, EDM-G-IMX8M-PLUS SOM - A bunch of Kontron boards update from Annette Kobou and Frieder Schrempf, adding overlay for LTE extension board, fixing GPIO for panel regulator, removing unused regulators, fixing USB hub reset and USB port etc. - A number of s32g updates from Dan Carpenter and Daniel Lezcano, adding OCOTP, timers and watchdog support - An i.MX95 update from Frank Li to add msi-map for pci-ep device - A series from Joy Zou to add i.MX91 support - A series from Krzysztof Kozlowski to add default GIC address cells for LS and i.MX8 SoCs - A set of changes from Peng Fan to improve i.MX95 support with more devices enabled - A series from Shengjiu Wang to support more sample rates for wm8524 card on i.MX8M EVK boards - Other random updates and cleanups on various boards * tag 'imx-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (75 commits) arm64: dts: s32g: Add device tree information for the OCOTP driver arm64: dts: add description for solidrun imx8mp hummingboard variants arm64: dts: imx8mm-phycore-som: optimize drive strengh arm64: dts: freescale: imx93-phycore-som: Remove "fsl,magic-packet" arm64: dts: freescale: imx93-phyboard-nash: Current sense via iio-hwmon arm64: dts: imx95: add standard PCI device compatible string to NETC Timer arm64: dts: freescale: add initial device tree for TQMa91xx/MBa91xxCA arm64: dts: imx93-11x11-evk: remove fec property eee-broken-1000t arm64: dts: freescale: add i.MX91 11x11 EVK basic support arm64: dts: imx91: add i.MX91 dtsi support arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and modify them arm64: dts: freescale: move aliases from imx93.dtsi to board dts arm64: dts: lx2160a-clearfog-itx: enable pcie nodes for x4 and x8 slots arm64: dts: lx2160a-cex7: add interrupts for rtc and ethernet phy arm64: dts: add description for solidrun imx8mp som and cubox-m arm64: dts: imx8: Use GIC_SPI for interrupt-map for readability arm64: dts: imx8qxp: Add default GIC address cells arm64: dts: imx8qm: Add default GIC address cells arm64: dts: imx8mq: Add default GIC address cells arm64: dts: imx8mp: Add default GIC address cells ... Link: https://lore.kernel.org/r/20250915132535.253859-3-shawnguo2@yeah.net Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'imx-dt-6.18' of ↵Arnd Bergmann82-407/+271
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt i.MX ARM device tree changes for 6.18: - A series from Alexander Stein to clean up the most of dt-schema warnings for LS1021A - A couple of changes from Bence Csókás to replace license text comment with SPDX identifier for imx6-display5 and imx6-aristainetos2 board - A couple of vfxxx dt-schema cleanups from Fabio Estevam - A bunch of changes from Frank Li to clean up dt-schema warnings on various platforms, VF610, LS1021A, i.MX6, etc. - Minor whitespace cleanup on i.MX8ULL from Krzysztof Kozlowski - An imx6ulz-bsh-smm-m2 workaround from Wolfgang Birkner to get resume via console work * tag 'imx-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits) ARM: dts: imx6sll: Use 'dma-names' ARM: dts: imx6: change rtc compatible string to st,m41t00 from m41t00 ARM: dts: imx6: remove undefined linux,default-trigger source ARM: dts: imx6ul-pico: add power-supply for vxt,vl050-8048nt-c01 ARM: dts: imx6ul-14x14-evk: add regulator for ov5640 ARM: dts: imx6: replace isl,isl12022 with isil,isl12022 for RTC ARM: dts: imx6: replace gpio-key with gpio-keys compatible string ARM: dts: imx6: rename i2c<n>mux i2c-mux-<n> ARM: dts: imx6: rename node name flash to eeprom ARM: dts: imx6: rename node i2c-gpio to i2c. ARM: dts: imx6: rename touch screen's node name to touchscreen ARM: dts: imx6: remove redundant pinctrl-names ARM: dts: imx6qdl-aristainetos2: rename ethernet-phy to ethernet-phy@0 ARM: dts: imx6: add interrupt-cells for dlg,da9063 pmic ARM: dts: imx6: align rtc chip node name to 'rtc' ARM: dts: imx6: add key- prefix for gpio-keys ARM: dts: imx6: add #address-cells for gsc@20 ARM: dts: imx6ul-tx6ul: Switch away from deprecated `phy-reset-gpios` ARM: dts: mba6ul: Add MicIn routing ARM: dts: ls1021a-tsn: Remove redundant #address-cells for ethernet-switch@1 ... Link: https://lore.kernel.org/r/20250915132535.253859-2-shawnguo2@yeah.net Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'imx-defconfig-6.18' of ↵Arnd Bergmann1-0/+2
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/defconfig i.MX defconfig changes for 6.18: - Enable i.MX91 pinctrl driver and Marvell WiFi-Ex USB driver in arm64 defconfig * tag 'imx-defconfig-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: defconfig: Enable Marvell WiFi-Ex USB driver arm64: defconfig: enable i.MX91 pinctrl Link: https://lore.kernel.org/r/20250915132535.253859-4-shawnguo2@yeah.net Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'microchip-soc-6.18' of ↵Arnd Bergmann1-14/+37
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/drivers Microchip ARM64 SoC updates for v6.18: This update includes: - basic infrastructure support for Microchip LAN969x SoC - SoC ARCH symbols (existing SparX-5, new LAN969x) under the ARCH_MICROCHIP hidden symbol (already in use by AT91 in 6.17) - addition of that new symbol for drivers that are shared by Microchip SoC-s now and in the future * tag 'microchip-soc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: crypto: atmel-aes: make it selectable for ARCH_MICROCHIP char: hw_random: atmel: make it selectable for ARCH_MICROCHIP i2c: at91: make it selectable for ARCH_MICROCHIP spi: atmel: make it selectable for ARCH_MICROCHIP tty: serial: atmel: make it selectable for ARCH_MICROCHIP mfd: at91-usart: Make it selectable for ARCH_MICROCHIP arm64: lan969x: Add support for Microchip LAN969x SoC arm64: Add config for Microchip SoC platforms Link: https://lore.kernel.org/r/20250915123548.13722-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'arm-soc/for-6.18/defconfig-arm64' of ↵Arnd Bergmann1-0/+2
https://github.com/Broadcom/stblinux into soc/defconfig This pull request contains ARM64 defconfig changes for Broadcom SoCs, please pull the following: - Andrea enables the RP1 pinctrl driver which is necessary for the Raspberry Pi 5 systems * tag 'arm-soc/for-6.18/defconfig-arm64' of https://github.com/Broadcom/stblinux: arm64: defconfig: Enable BCM2712 on-chip pin controller driver Link: https://lore.kernel.org/r/20250910171910.666401-1-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'samsung-defconfig-6.18' of ↵Arnd Bergmann2-1/+1
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/defconfig Samsung SoC defconfig changes for v6.18 1. Cleanup MTD_NAND_S3C2410, being removed from the kernel via separate tree. 2. Enable Axis ARTPEC SoC in arm64 defconfig - new Samsung subarch. * tag 'samsung-defconfig-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: defconfig: Enable Axis ARTPEC SoC ARM: s3c6400_defconfig: Drop MTD_NAND_S3C2410 Link: https://lore.kernel.org/r/20250909180127.99783-3-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'aspeed-6.18-devicetree-1' of ↵Arnd Bergmann22-73/+1359
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt Further ASPEED devicetree updates for v6.18 New platforms: - Meta Clemente Clemente is a compute-tray platform using an AST2600 SoC Updated platforms: - Harma (Meta): Hot-swap controller, power monitoring, GPIO names There are also some devicetree cleanups from Rob and Krzysztof that touch a variety of platforms and the DTSIs. These lead to fewer warnings emitted for the ASPEED devicetrees. * tag 'aspeed-6.18-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: ARM: dts: aspeed: Drop syscon "reg-io-width" properties ARM: dts: aspeed: Drop "sdhci" compatibles ARM: dts: aspeed: Fix/add I2C device vendor prefixes ARM: dts: aspeed: Minor whitespace cleanup ARM: dts: aspeed: clemente: add Meta Clemente BMC ARM: dts: aspeed: Add NCSI3 and NCSI4 pinctrl nodes dt-bindings: arm: aspeed: add Meta Clemente board ARM: dts: aspeed: harma: add mp5990 ARM: dts: aspeed: harma: revise gpio name ARM: dts: aspeed: harma: add power monitor support Link: https://lore.kernel.org/r/5793039afcedeb28179a3c9909631d8251abc73e.camel@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'tegra-for-6.18-arm64-dt' of ↵Arnd Bergmann1-0/+225
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v6.18-rc1 Add I2C nodes for Tegra264. These are currently unused but are needed for subsequent audio patches, as well as various monitoring and other auxiliary chips. * tag 'tegra-for-6.18-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add I2C nodes for Tegra264 Link: https://lore.kernel.org/r/20250914063927.89981-4-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.0) at 2026-06-09 13:28:39 +0300