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2025-10-13KVM: arm64: Kill leftovers of ad-hoc timer userspace accessMarc Zyngier2-123/+0
Now that the whole timer infrastructure is handled as system register accesses, get rid of the now unused ad-hoc infrastructure. Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Fix WFxT handling of nested virtMarc Zyngier1-1/+6
The spec for WFxT indicates that the parameter to the WFxT instruction is relative to the reading of CNTVCT_EL0. This means that the implementation needs to take the execution context into account, as CNTVOFF_EL2 does not always affect readings of CNTVCT_EL0 (such as when HCR_EL2.E2H is 1 and that we're in host context). This also rids us of the last instance of KVM_REG_ARM_TIMER_CNT outside of the userspace interaction code. Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Move CNT*CT_EL0 userspace accessors to generic infrastructureMarc Zyngier2-10/+31
Moving the counter registers is a bit more involved than for the control and comparator (there is no shadow data for the counter), but still pretty manageable. Reviewed-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Move CNT*_CVAL_EL0 userspace accessors to generic infrastructureMarc Zyngier2-8/+4
As for the control registers, move the comparator registers to the common infrastructure. Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Move CNT*_CTL_EL0 userspace accessors to generic infrastructureMarc Zyngier2-9/+31
Remove the handling of CNT*_CTL_EL0 from guest.c, and move it to sys_regs.c, using a new TIMER_REG() definition to encapsulate it. Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Add timer UAPI workaround to sysreg infrastructureMarc Zyngier2-3/+36
Amongst the numerous bugs that plague the KVM/arm64 UAPI, one of the most annoying thing is that the userspace view of the virtual timer has its CVAL and CNT encodings swapped. In order to reduce the amount of code that has to know about this, start by adding handling for this bug in the sys_reg code. Nothing is making use of it yet, as the code responsible for userspace interaction is catching the accesses early. Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Make timer_set_offset() generally accessibleMarc Zyngier1-10/+0
Move the timer_set_offset() helper to arm_arch_timer.h, so that it is next to timer_get_offset(), and accessible by the rest of KVM. Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Replace timer context vcpu pointer with timer_idMarc Zyngier1-2/+2
Having to follow a pointer to a vcpu is pretty dumb, when the timers are are a fixed offset in the vcpu structure itself. Trade the vcpu pointer for a timer_id, which can then be used to compute the vcpu address as needed. Reviewed-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Introduce timer_context_to_vcpu() helperMarc Zyngier1-12/+13
We currently have a vcpu pointer nested into each timer context. As we are about to remove this pointer, introduce a helper (aptly named timer_context_to_vcpu()) that returns this pointer, at least until we repaint the data structure. Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Hide CNTHV_*_EL2 from userspace for nVHE guestsMarc Zyngier1-13/+13
Although we correctly UNDEF any CNTHV_*_EL2 access from the guest when E2H==0, we still expose these registers to userspace, which is a bad idea. Drop the ad-hoc UNDEF injection and switch to a .visibility() callback which will also hide the register from userspace. Fixes: 0e45981028550 ("KVM: arm64: timer: Don't adjust the EL2 virtual timer offset") Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: gic-v3: Only set ICH_HCR traps for v2-on-v3 or v3 guestsSascha Bischoff1-1/+4
The ICH_HCR_EL2 traps are used when running on GICv3 hardware, or when running a GICv3-based guest using FEAT_GCIE_LEGACY on GICv5 hardware. When running a GICv2 guest on GICv3 hardware the traps are used to ensure that the guest never sees any part of GICv3 (only GICv2 is visible to the guest), and when running a GICv3 guest they are used to trap in specific scenarios. They are not applicable for a GICv2-native guest, and won't be applicable for a(n upcoming) GICv5 guest. The traps themselves are configured in the vGIC CPU IF state, which is stored as a union. Updating the wrong aperture of the union risks corrupting state, and therefore needs to be avoided at all costs. Bail early if we're not running a compatible guest (GICv2 on GICv3 hardware, GICv3 native, GICv3 on GICv5 hardware). Trap everything unconditionally if we're running a GICv2 guest on GICv3 hardware. Otherwise, conditionally set up GICv3-native trapping. Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Guard PMSCR_EL1 initialization with SPE presence checkMukesh Ojha1-5/+10
Commit efad60e46057 ("KVM: arm64: Initialize PMSCR_EL1 when in VHE") does not perform sufficient check before initializing PMSCR_EL1 to 0 when running in VHE mode. On some platforms, this causes the system to hang during boot, as EL3 has not delegated access to the Profiling Buffer to the Non-secure world, nor does it reinject an UNDEF on sysreg trap. To avoid this issue, restrict the PMSCR_EL1 initialization to CPUs that support Statistical Profiling Extension (FEAT_SPE) and have the Profiling Buffer accessible in Non-secure EL1. This is determined via a new helper `cpu_has_spe()` which checks both PMSVer and PMBIDR_EL1.P. This ensures the initialization only affects CPUs where SPE is implemented and usable, preventing boot failures on platforms where SPE is not properly configured. Fixes: efad60e46057 ("KVM: arm64: Initialize PMSCR_EL1 when in VHE") Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13riscv: dts: spacemit: define regulator constraintsAlex Elder1-0/+104
Define basic constraints for the regulators in the SpacemiT P1 PMIC, as implemented in the Banana Pi BPI-F3. Signed-off-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/r/20250825172057.163883-8-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-10-13riscv: dts: spacemit: define fixed regulatorsAlex Elder1-0/+19
Define the DC power input and the 4v power as fixed supplies in the Banana Pi BPI-F3. Signed-off-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/r/20250825172057.163883-7-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-10-13riscv: dts: spacemit: enable the i2c8 adapterAlex Elder3-0/+32
Define properties for the I2C adapter that provides access to the SpacemiT P1 PMIC. Enable this adapter on the Banana Pi BPI-F3. Signed-off-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/r/20250825172057.163883-6-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-10-13KVM: arm64: Remove unreachable break after returnOsama Abdelkader1-1/+0
Remove an unnecessary 'break' statement that follows a 'return' in arch/arm64/kvm/at.c. The break is unreachable. Signed-off-by: Osama Abdelkader <osama.abdelkader@gmail.com> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Prevent access to vCPU events before initOliver Upton1-0/+6
Another day, another syzkaller bug. KVM erroneously allows userspace to pend vCPU events for a vCPU that hasn't been initialized yet, leading to KVM interpreting a bunch of uninitialized garbage for routing / injecting the exception. In one case the injection code and the hyp disagree on whether the vCPU has a 32bit EL1 and put the vCPU into an illegal mode for AArch64, tripping the BUG() in exception_target_el() during the next injection: kernel BUG at arch/arm64/kvm/inject_fault.c:40! Internal error: Oops - BUG: 00000000f2000800 [#1] SMP CPU: 3 UID: 0 PID: 318 Comm: repro Not tainted 6.17.0-rc4-00104-g10fd0285305d #6 PREEMPT Hardware name: linux,dummy-virt (DT) pstate: 21402009 (nzCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--) pc : exception_target_el+0x88/0x8c lr : pend_serror_exception+0x18/0x13c sp : ffff800082f03a10 x29: ffff800082f03a10 x28: ffff0000cb132280 x27: 0000000000000000 x26: 0000000000000000 x25: ffff0000c2a99c20 x24: 0000000000000000 x23: 0000000000008000 x22: 0000000000000002 x21: 0000000000000004 x20: 0000000000008000 x19: ffff0000c2a99c20 x18: 0000000000000000 x17: 0000000000000000 x16: 0000000000000000 x15: 00000000200000c0 x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 x11: 0000000000000000 x10: 0000000000000000 x9 : 0000000000000000 x8 : ffff800082f03af8 x7 : 0000000000000000 x6 : 0000000000000000 x5 : ffff800080f621f0 x4 : 0000000000000000 x3 : 0000000000000000 x2 : 000000000040009b x1 : 0000000000000003 x0 : ffff0000c2a99c20 Call trace: exception_target_el+0x88/0x8c (P) kvm_inject_serror_esr+0x40/0x3b4 __kvm_arm_vcpu_set_events+0xf0/0x100 kvm_arch_vcpu_ioctl+0x180/0x9d4 kvm_vcpu_ioctl+0x60c/0x9f4 __arm64_sys_ioctl+0xac/0x104 invoke_syscall+0x48/0x110 el0_svc_common.constprop.0+0x40/0xe0 do_el0_svc+0x1c/0x28 el0_svc+0x34/0xf0 el0t_64_sync_handler+0xa0/0xe4 el0t_64_sync+0x198/0x19c Code: f946bc01 b4fffe61 9101e020 17fffff2 (d4210000) Reject the ioctls outright as no sane VMM would call these before KVM_ARM_VCPU_INIT anyway. Even if it did the exception would've been thrown away by the eventual reset of the vCPU's state. Cc: stable@vger.kernel.org # 6.17 Fixes: b7b27facc7b5 ("arm/arm64: KVM: Add KVM_GET/SET_VCPU_EVENTS") Signed-off-by: Oliver Upton <oliver.upton@linux.dev> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: Use the in-context stage-1 in __kvm_find_s1_desc_level()Oliver Upton1-1/+5
Running the external_aborts selftest at EL2 leads to an ugly splat due to the stage-1 MMU being disabled for the walked context, owing to the fact that __kvm_find_s1_desc_level() is hardcoded to the EL1&0 regime. Select the appropriate translation regime for the stage-1 walk based on the current vCPU context. Fixes: b8e625167a32 ("KVM: arm64: Add S1 IPA to page table level walker") Signed-off-by: Oliver Upton <oliver.upton@linux.dev> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: nv: Don't advance PC when pending an SVE exceptionMarc Zyngier1-1/+1
Jan reports that running a nested guest on Neoverse-V2 leads to a WARN in the host due to simultaneously pending an exception and PC increment after an access to ZCR_EL2. Returning true from a sysreg accessor is an indication that the sysreg instruction has been retired. Of course this isn't the case when we've pended a synchronous SVE exception for the guest. Fix the return value and let the exception propagate to the guest as usual. Reported-by: Jan Kotas <jank@cadence.com> Closes: https://lore.kernel.org/kvmarm/865xd61tt5.wl-maz@kernel.org/ Signed-off-by: Oliver Upton <oliver.upton@linux.dev> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13KVM: arm64: nv: Don't treat ZCR_EL2 as a 'mapped' registerOliver Upton1-4/+2
Unlike the other mapped EL2 sysregs ZCR_EL2 isn't guaranteed to be resident when a vCPU is loaded as it actually follows the SVE context. As such, the contents of ZCR_EL1 may belong to another guest if the vCPU has been preempted before reaching sysreg emulation. Unconditionally use the in-memory value of ZCR_EL2 and switch to the memory-only accessors. The in-memory value is guaranteed to be valid as fpsimd_lazy_switch_to_{guest,host}() will restore/save the register appropriately. Signed-off-by: Oliver Upton <oliver.upton@linux.dev> Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-10-13riscv: dts: spacemit: add UART pinctrl combinationsHendrik Hamerlinck1-2/+428
Add UART pinctrl configurations based on the SoC datasheet and the downstream Bianbu Linux tree. The drive strength values were taken from the downstream implementation, which uses medium drive strength. CTS/RTS are moved to separate *-cts-rts-cfg states so boards can enable hardware flow control conditionally. Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20250917065907.160615-1-hendrik.hamerlinck@hammernet.be Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-10-13arm64: dts: mediatek: Add MT6878 pinmux macro header fileIgor Belwon1-0/+1201
Add the required macros for the pinmux nodes of the MediaTek MT6878 SoC. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13arm64: dts: marvell: pxa1908: Add power domainsDuje Mihanović2-1/+5
Update the APMU clock controller's compatible to allow the new power domain driver to probe. Also add the first two power domain consumers: IOMMU (fixes probing) and framebuffer. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Add USB connectorDuje Mihanović1-0/+6
Add a node for the micro-USB connector found on the board. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Fill in memory nodeDuje Mihanović1-2/+11
The board is known to have 1 GiB of DRAM with the first 16 MiB unusable. Instead of relying on the bootloader to fill in the memory node, do it ourselves. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Drop some reserved memoryDuje Mihanović1-17/+0
Most of the memory marked as reserved is actually usable. Delete its reserved-memory nodes so that the memory can be used. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: pxa1908: Move ramoops to SoC dtsiDuje Mihanović2-12/+14
The ramoops memory region is the same for all boards based on the SoC. Move its node to the appropriate dtsi. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Add vibratorDuje Mihanović1-0/+23
The board has a vibrator hooked up to PWM3. Add a node for it and its associated pinctrl configuration. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: pxa1908: Add PWMsDuje Mihanović1-0/+32
The SoC has 4 onboard PWMs. Add a node for each of them. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Enable eMMCDuje Mihanović1-2/+77
Commit a41fcca4b342 ("mmc: sdhci-pxav3: set NEED_RSP_BUSY capability") fixed eMMC probing on this board. Enable the eMMC and add its pinctrl. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Correct CD GPIODuje Mihanović1-2/+1
Right now, the CD GPIO is defined as active high with a cd-inverted property. Just define the GPIO as active low instead. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Add backlightDuje Mihanović1-0/+6
Add a node for the KTD2801 backlight chip found on the board. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: samsung,coreprimevelte: add SDIOKarel Balej1-0/+71
Set some basic properties of the SDIO card of the samsung,coreprimevelte smartphone. The SDIO is used as an interface for WiFi, Bluetooth and FM radio serviced by the Marvell 88W8777 (SD8777) chipset. Support for this chipset is currently not in-tree because the firmware is not available in linux-firmware, however it is possible to trivially run it out-of-tree using the mwifiex and Marvell Bluetooth drivers with some caveats. Link: https://lore.kernel.org/r/20231029111807.19261-1-balejk@matfyz.cz/ Signed-off-by: Karel Balej <balejk@matfyz.cz> Reviewed-by: Duje Mihanović <duje@dujemihanovic.xyz> [Duje: fix formatting of pins_0 and fast_pins_1 pin arrays] Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: samsung,coreprimevelte: add touchscreenKarel Balej1-0/+15
Bind touchscreen for the samsung,coreprimevelte smartphone. The downstream code sets the VDD voltage to the exact value of 3.1 V, however it's been empirically verified that the lower bound used here sufficies for the proper operation of the chip and is thus used for power-saving purposes. Signed-off-by: Karel Balej <balejk@matfyz.cz> Reviewed-by: Duje Mihanović <duje@dujemihanovic.xyz> Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: samsung,coreprimevelte: add PMICKarel Balej1-0/+23
Bind power management chip to the samsung,coreprimevelte smartphone. This enables support for onkey and RTC as well as for regulators two of which are explicitly bound here to the SD card. Signed-off-by: Karel Balej <balejk@matfyz.cz> Reviewed-by: Duje Mihanović <duje@dujemihanovic.xyz> Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13ARM: dts: mediatek: add basic support for Alcatel yarisxl boardCristian Cozzolino2-0/+62
This smartphone uses a MediaTek MT6582 system-on-chip with 512MB of RAM. It can currently boot into initramfs with a working UART and Simple Framebuffer using already initialized panel by the bootloader. Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13ARM: dts: mediatek: mt6582: add enable-method property to cpusCristian Cozzolino1-0/+1
Add missing property for SMP. Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13ARM: dts: mediatek: mt6582: add clock-names property to uart nodesCristian Cozzolino1-0/+4
Other SoC DTSI files define this property for their uart nodes. Do the same here too, to be consistent. Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13ARM: dts: mediatek: mt6582: add mt6582 compatible to timerCristian Cozzolino1-3/+2
Bindings already have mt6582 compatible for timer, so add that to DTSI. While at it, remove clock-names property (which is not required by timer node) and fix node address. Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13ARM: dts: mediatek: mt6582: remove compatible property from root nodeCristian Cozzolino1-1/+0
SoC's DTSI does not require compatible property. Drop that. Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13ARM: dts: mediatek: mt6582: sort nodes and propertiesCristian Cozzolino1-26/+20
Sort fixed clocks nodes by clock frequency and memory mapped device nodes by reg address. Also, sort properties as shown in dt-bindings examples. Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13ARM: dts: mediatek: mt6582: move MMIO devices under soc nodeCristian Cozzolino1-61/+68
Memory mapped devices are part of soc. So, add such node and move those devices into it. Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13ARM: mediatek: add MT6582 smp bring up codeCristian Cozzolino2-0/+5
Add support for booting secondary CPUs on MT6582. Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13ARM: mediatek: add board_dt_compat entry for the MT6582 SoCCristian Cozzolino1-0/+1
Add a compatible string for the MT6582 SoC. Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13arm64: dts: mediatek: mt7986-bpi-r3: Change fan PWM value for mid speedMikhail Kshevetskiy1-1/+1
Popular cheap PWM fans for this machine, like the ones coming in heatsink+fan combos will not work properly at the currently defined medium speed. Trying different pwm setting using a command echo $value > /sys/devices/platform/pwm-fan/hwmon/hwmon1/pwm1 I found: pwm1 value fan rotation speed cpu temperature notes ----------------------------------------------------------------- 0 maximal 31.5 Celsius too noisy 40 optimal 35.2 Celsius no noise hearable 95 minimal above 95 does not rotate 55.5 Celsius ----------------------------------------------------------------- Thus only cpu-active-high and cpu-active-low modes are usable. I think this is wrong. This patch fixes cpu-active-medium settings for bpi-r3 board. I know, the patch is not ideal as it can break pwm fan for some users. Likely this is the only official mt7986-bpi-r3 heatsink+fan solution available on the market. This patch may not be enough. Users may wants to tweak their thermal_zone0 trip points, thus tuning fan rotation speed depending on cpu temperature. That can be done on the base of the following example: === example ========= # cpu temperature below 25 Celsius degrees, no rotation echo 25000 > /sys/class/thermal/thermal_zone0/trip_point_4_temp # cpu temperature in [25..32] Celsius degrees, normal rotation speed echo 32000 > /sys/class/thermal/thermal_zone0/trip_point_3_temp # cpu temperature above 50 Celsius degrees, max rotation speed echo 50000 > /sys/class/thermal/thermal_zone0/trip_point_2_temp ===================== Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Acked-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510Bartosz Bilas2-0/+21
Add support for Grinn GenioSBC-510. Based on the commit introducing support for the Grinn GenioSBC-700, this change adds support for the Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio 510 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-510 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700Mateusz Koza4-0/+769
Add support for Grinn GenioSBC-700. The Grinn GenioSBC-700 is a single-board computer based on the MediaTek Genio 700 SoC. Its device tree is split into separate SoM (.dtsi) and SBC (.dtsi) files, which are combined in the SoC-specific .dts file. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13arm64: dts: renesas: eagle-function-expansion: Add eMMC supportWolfram Sang1-0/+17
Add pinmuxing and configuration of the MMC-capable SDHI instance to make use of the eMMC. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250923161709.3110-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-13arm64: defconfig: Enable UFS support for MediaTek Genio 1200 EVK UFS boardMacpaul Lin1-0/+1
Enable the UFS related settings to support Genio 1200 EVK UFS board. This board uses UFS as the boot device and also the main storage. This includes support for: - CONFIG_SCSI_UFS_MEDIATEK Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-13arm64: dts: mediatek: mt7988a: add 'soc-uuid' cell to efuseDaniel Golle1-0/+4
The efuse of the MediaTek MT7988 contains a 16-byte unique identifier. Add a 'soc-uuid' cell covering those 16 bytes to the nvmem defininition of the efuse to allow easy access from userspace, eg. to generate a persistent random MAC address on boards like the BananaPi R4 which doesn't have any factory-assigned addresses. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-06-07 19:21:35 +0300