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2025-11-14s390/pai_crypto: Rename structure paicrypt_mapptr to pai_mapptrThomas Richter1-12/+12
To support one common PAI PMU device driver which handles both PMUs pai_crypto and pai_ext, use a common naming scheme for structures and variables suitable for both device drivers. Rename structure paicrypt_mapptr to pai_mapptr. No functional change. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Reviewed-by: Jan Polensky <japo@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
2025-11-14s390/pai_crypto: Rename member paicrypt_map::pageThomas Richter1-10/+10
Rename member page in struct paicrypt_map to area. This rename creates consistent naming for both PMU drivers paicrypto and PMU paiext. No functional change. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Reviewed-by: Jan Polensky <japo@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
2025-11-14s390/pai_crypto: Rename variable cfm_dbgThomas Richter1-8/+8
The global variable cfm_dbg points to the s390dbf debug buffer. Rename it to paidbg to better reflect its purpose. No functional change. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Reviewed-by: Jan Polensky <japo@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
2025-11-14syscore: Pass context data to callbacksThierry Reding41-176/+344
Several drivers can benefit from registering per-instance data along with the syscore operations. To achieve this, move the modifiable fields out of the syscore_ops structure and into a separate struct syscore that can be registered with the framework. Add a void * driver data field for drivers to store contextual data that will be passed to the syscore ops. Acked-by: Rafael J. Wysocki (Intel) <rafael@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14arm64: dts: st: set RIFSC as an access controller on stm32mp21x platformsGatien Chevallier1-1/+3
Similarly to stm32mp23x/25x platforms, the RIFSC is a firewall controller. Declare it as an access controller, keep the "simple-bus" compatible in case CONFIG_STM32_FIREWALL is not set and update the child nodes. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20251106-rifsc_debugfs-v2-2-f90e94ae756d@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-11-14ARM: dts: stm32: add the IWDG2 interrupt line in stm32mp131.dtsiGatien Chevallier1-0/+1
Add the interrupt line that can be used for the early interrupt of the IWDG2 to the IWDG2 node Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20251031-iwdg1-v2-4-2dc6e0116725@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-11-14ARM: dts: stm32: enable the ARM SMC watchdog node in stm32mp135f-dkGatien Chevallier1-0/+5
On the stm32mp135f-dk board, the IWDG1 is secured and used to monitor the cortex-A7. Use the ARM SMC watchdog to communicate with it. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20251031-iwdg1-v2-3-2dc6e0116725@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-11-14ARM: dts: stm32: add the ARM SMC watchdog in stm32mp131.dtsiGatien Chevallier1-0/+6
Add the arm_wdt node in the stm32mp131.dtsi SoC device tree file. When the platform watchdog is managed by the secure world, SMC calls are used to interact with it. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20251031-iwdg1-v2-2-2dc6e0116725@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-11-14ARM: dts: stm32: add iwdg1 node in stm32mp131.dtsiGatien Chevallier1-0/+10
Add the IWDG1 node in the stm32mp131.dtsi SoC device tree file. It can be used by Linux as the Cortex-A7 watchdog when it's configured as non-secure. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20251031-iwdg1-v2-1-2dc6e0116725@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-11-14arm64: dts: st: Add I/O sync to eth pinctrl in stm32mp25-pinctrl.dtsiAntonio Borneo1-0/+4
On board stm32mp257f-ev1, the propagation delay between eth1/eth2 and the external PHY requires a compensation to guarantee that no packet get lost in all the working conditions. Add I/O synchronization properties in pinctrl on all the RGMII data pins, activating re-sampling on both edges of the clock. Co-developed-by: Christophe Roullier <christophe.roullier@foss.st.com> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20251023132700.1199871-13-antonio.borneo@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-11-14arm64: dts: st: Add memory-region-names property for stm32mp257f-ev1Patrice Chotard1-0/+1
In order to set the AMCR register, which configures the memory-region split between ospi1 and ospi2, we need to identify the ospi instance. By using memory-region-names, it allows to identify the ospi instance this memory-region belongs to. Fixes: cad2492de91c ("arm64: dts: st: Add SPI NOR flash support on stm32mp257f-ev1 board") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20251031-upstream_fix_dts_omm-v4-1-e4a059a50074@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-11-14powerpc/smp: Expose die_id and die_cpumaskSrikar Dronamraju2-4/+30
>From Power10 processors onwards, each chip has 2 hemispheres. For LPARs running on PowerVM Hypervisor, hypervisor determines the allocation of CPU groups to each LPAR, resulting in two LPARs with the same number of CPUs potentially having different numbers of CPUs from each hemisphere. Additionally, it is not feasible to ascertain the hemisphere based solely on the CPU number. Users wishing to assign their workload to all CPUs, or a subset of CPUs within a specific hemisphere, encounter difficulties in identifying the cpumask. To address this, it is proposed to expose hemisphere information as a die in sysfs. This aligns with other architectures and facilitates the identification of CPUs within the same hemisphere. Tools such as lstopo can also access this information. Please note: The hypervisor reveals the locality of the CPUs to hemispheres only in dedicated mode. Consequently, in systems where hemisphere information is unavailable, such as shared LPARs, the die_cpus information in sysfs will mirror package_cpus, with die_id set to -1. Without this change. $ grep . /sys/devices/system/cpu/cpu16/topology/{die*,package*} 2>/dev/null /sys/devices/system/cpu/cpu16/topology/package_cpus:000000,000000ff,ffff0000 /sys/devices/system/cpu/cpu16/topology/package_cpus_list:16-39 With this change. $ grep . /sys/devices/system/cpu/cpu16/topology/{die*,package*} 2>/dev/null /sys/devices/system/cpu/cpu16/topology/die_cpus:000000,00000000,00ff0000 /sys/devices/system/cpu/cpu16/topology/die_cpus_list:16-23 /sys/devices/system/cpu/cpu16/topology/die_id:2 /sys/devices/system/cpu/cpu16/topology/package_cpus:000000,000000ff,ffff0000 /sys/devices/system/cpu/cpu16/topology/package_cpus_list:16-39 snipped lstopo-no-graphics o/p Group0 L#0 (total=8747584KB) Package L#0 (total=3564096KB CPUModel="POWER10 (architected), altivec supported" CPURevision="2.0 (pvr 0080 0200)") NUMANode L#0 (P#0 local=3564096KB total=3564096KB) Die L#0 (P#0) Core L#0 (P#0) <snipped> Package L#1 (total=5183488KB CPUModel="POWER10 (architected), altivec supported" CPURevision="2.0 (pvr 0080 0200)") NUMANode L#1 (P#1 local=5183488KB total=5183488KB) Die L#2 (P#2) Core L#2 (P#16) L3Cache L#4 (size=4096KB linesize=128 ways=16) L2Cache L#4 (size=1024KB linesize=128 ways=8) L1dCache L#4 (size=32KB linesize=128 ways=8) L1iCache L#4 (size=48KB linesize=128 ways=6) PU L#16 (P#16) PU L#17 (P#18) PU L#18 (P#20) PU L#19 (P#22) L3Cache L#5 (size=4096KB linesize=128 ways=16) L2Cache L#5 (size=1024KB linesize=128 ways=8) L1dCache L#5 (size=32KB linesize=128 ways=8) L1iCache L#5 (size=48KB linesize=128 ways=6) PU L#20 (P#17) PU L#21 (P#19) PU L#22 (P#21) PU L#23 (P#23) Die L#3 (P#3) Core L#3 (P#24) L3Cache L#6 (size=4096KB linesize=128 ways=16) L2Cache L#6 (size=1024KB linesize=128 ways=8) L1dCache L#6 (size=32KB linesize=128 ways=8) L1iCache L#6 (size=48KB linesize=128 ways=6) PU L#24 (P#24) PU L#25 (P#26) PU L#26 (P#28) PU L#27 (P#30) L3Cache L#7 (size=4096KB linesize=128 ways=16) L2Cache L#7 (size=1024KB linesize=128 ways=8) L1dCache L#7 (size=32KB linesize=128 ways=8) L1iCache L#7 (size=48KB linesize=128 ways=6) PU L#28 (P#25) PU L#29 (P#27) PU L#30 (P#29) PU L#31 (P#31) Core L#4 (P#32) L3Cache L#8 (size=4096KB linesize=128 ways=16) L2Cache L#8 (size=1024KB linesize=128 ways=8) L1dCache L#8 (size=32KB linesize=128 ways=8) L1iCache L#8 (size=48KB linesize=128 ways=6) PU L#32 (P#32) PU L#33 (P#34) PU L#34 (P#36) PU L#35 (P#38) L3Cache L#9 (size=4096KB linesize=128 ways=16) L2Cache L#9 (size=1024KB linesize=128 ways=8) L1dCache L#9 (size=32KB linesize=128 ways=8) L1iCache L#9 (size=48KB linesize=128 ways=6) PU L#36 (P#33) PU L#37 (P#35) PU L#38 (P#37) PU L#39 (P#39) Group0 L#1 (total=7736896KB) Package L#2 (total=5170880KB CPUModel="POWER10 (architected), altivec supported" CPURevision="2.0 (pvr 0080 0200)") NUMANode L#2 (P#2 local=5170880KB total=5170880KB) Die L#4 (P#4) <snipped> Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com> Signed-off-by: Srikar Dronamraju <srikar@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20251112074859.814087-1-srikar@linux.ibm.com
2025-11-14Merge tag 'acpi-6.18-rc6' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull ACPI fixes from Rafael Wysocki: "These fix issues in the ACPI CPPC library and in the recently added parser for the ACPI MRRM table: - Limit some checks in the ACPI CPPC library to online CPUs to avoid accessing uninitialized per-CPU variables when some CPUs are offline to start with, like during boot with 'nosmt=force' (Gautham Shenoy) - Rework add_boot_memory_ranges() in the ACPI MRRM table parser to fix memory leaks and improve error handling (Kaushlendra Kumar)" * tag 'acpi-6.18-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: ACPI: MRRM: Fix memory leaks and improve error handling ACPI: CPPC: Limit perf ctrs in PCC check only to online CPUs ACPI: CPPC: Perform fast check switch only for online CPUs ACPI: CPPC: Check _CPC validity for only the online CPUs ACPI: CPPC: Detect preferred core availability on online CPUs
2025-11-14arm64: dts: rockchip: fix PCIe 3.3V regulator voltage on orangepi-5Mykola Kvach1-2/+2
The vcc3v3_pcie20 fixed regulator powers the PCIe device-side 3.3V rail for pcie2x1l2 via vpcie3v3-supply. The DTS mistakenly set its regulator-min/max-microvolt to 1800000 (1.8 V). Correct both to 3300000 (3.3 V) to match the rail name, the PCIe/M.2 power requirement, and the actual hardware wiring on Orange Pi 5. Fixes: b6bc755d806e ("arm64: dts: rockchip: Add Orange Pi 5") Cc: stable@vger.kernel.org Signed-off-by: Mykola Kvach <xakep.amatop@gmail.com> Reviewed-by: Michael Riesch <michael.riesch@collabora.com> Link: https://patch.msgid.link/cf6e08dfdfbf1c540685d12388baab1326f95d2c.1762165324.git.xakep.amatop@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: disable HS400 on RK3588 TigerQuentin Schulz1-3/+1
We've had reports from the field that some RK3588 Tiger have random issues with eMMC errors. Applying commit a28352cf2d2f ("mmc: sdhci-of-dwcmshc: Change DLL_STRBIN_TAPNUM_DEFAULT to 0x4") didn't help and seemed to have made things worse for our board. Our HW department checked the eMMC lines and reported that they are too long and don't look great so signal integrity is probably not the best. Note that not all Tigers with the same eMMC chip have errors, so the suspicion is that we're really on the edge in terms of signal integrity and only a handful devices are failing. Additionally, we have RK3588 Jaguars with the same eMMC chip but the layout is different and we also haven't received reports about those so far. Lowering the max-frequency to 150MHz from 200MHz instead of simply disabling HS400 was briefly tested and seem to work as well. We've disabled HS400 downstream and haven't received reports since so we'll go with that instead of lowering the max-frequency. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Fixes: 6173ef24b35b ("arm64: dts: rockchip: add RK3588-Q7 (Tiger) SoM") Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20251112-tiger-hs200-v1-1-b50adac107c0@cherry.de [added Fixes tag and stable-cc from 2nd mail] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: fixes ethernet for 100ASK DshanPi A1Chukun Pan1-8/+7
Currently, Ethernet is unusable due to an incorrect PHY address. This commit fixes this, removes the incorrect 25M clock pinctrl, and adds the missing PHY supply. Fixes: d809417c5a40 ("arm64: dts: rockchip: add DTs for 100ASK DShanPi A1") Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://patch.msgid.link/20251101120010.41729-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: fixes regulator for 100ASK DshanPi A1Chukun Pan1-43/+3
Referencing the schematic [1], correct the names of the USB regulator, remove these non-existent RTC and UFS regulators. [1] https://dl.100ask.net/Hardware/MPU/RK3576-DshanPi-A1/DshanPi-A1-RK3576-SCH_V1.1.pdf Fixes: d809417c5a40 ("arm64: dts: rockchip: add DTs for 100ASK DShanPi A1") Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://patch.msgid.link/20251101120010.41729-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: drop reset from rk3576 i2c9 nodeChukun Pan1-2/+0
The reset property is not part of the binding, so drop it. It is also not used by the driver, so it was likely copied from some vendor-kernel node. Fixes: 57b1ce903966 ("arm64: dts: rockchip: Add rk3576 SoC base DT") Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://patch.msgid.link/20251101140101.302229-1-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: correct assigned-clock-rates spelling on 2 boardsJohan Jonker2-2/+2
Due to some copy and paste from the manufacturer tree the property assigned-clock-rate is missing a letter "s". Correct spelling to reduce dtbs_check output. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://patch.msgid.link/92714b6c-6c0d-4a10-afe4-73ed313c87c0@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14ARM: dts: rockchip: move edp assigned-clocks to edp node on rk3288Johan Jonker1-3/+2
The rk3288 power-controller node contains an assigned-clocks property that conflicts with the bindings. From the git history it shows that they wanted to assign the rk3288 EDP_24M clock input centrally before an edp node was available. Move the edp assigned-clocks property to the edp node to reduce dtbs_check output. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://patch.msgid.link/7d6fa223-ab90-4c44-9180-54df78467ea5@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: clean up devicetree for 9Tripod X3568 v4Coia Prant1-16/+9
Fix indentation, remove unused SDIO properties, and drop the GMAC clock that was used for input direction. The board uses the clock as output, so the input clock is not needed. Signed-off-by: Coia Prant <coiaprant@gmail.com> Link: https://patch.msgid.link/20251107133839.300252-1-coiaprant@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: Enable USB-C DP Alt for Indiedroid NovaChris Morgan1-13/+67
Enable the Display Port alt-mode for the USB-C port on the Indiedroid Nova. Note that while ROCKCHIP_VOP2_EP_DP0 is defined as 10 we need to set the address to "a" or else we receive a dtc warning. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://patch.msgid.link/20251107214724.878955-1-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: add eMMC CQE support for rk3588Sebastian Reichel1-0/+1
The RK3588 eMMC controller supports CQE, so add the missing DT flag. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://patch.msgid.link/20251031-rockchip-emmc-cqe-support-v2-2-958171f5edad@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: enable HDMI audio on Rock 5 ITXTorsten Duwe1-0/+9
The Rock 5 ITX only needs enablement for 2 nodes in order to send audio on HDMI1, the connector closer to the 12V barrel jack and farther from S/PDIF. It is sufficient to declare the audio injection as okay, and to activate I2S6. Note that for the other HDMI output it is not that trivial, as the video data there originates from the SoC's DisplayPort output DP1 and is only converted to HDMI in U7 (an RA620). Signed-off-by: Torsten Duwe <duwe@lst.de> [fixed commit subject prefixes] Link: https://patch.msgid.link/20251110181153.CC62B6732A@verein.lst.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 3CFUKAUMI Naoki1-0/+1
The VCC supply for the BL24C16 EEPROM chip found on Radxa ROCK 3C is vcca1v8_pmu. [1] Describe this supply. [1] https://dl.radxa.com/rock3/docs/hw/3c/v1400/radxa_rock_3c_v1400_schematic.pdf p.13 Fixes: ee219017ddb50 ("arm64: dts: rockchip: Add Radxa ROCK 3C") Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://patch.msgid.link/20251112035133.28753-4-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 5AFUKAUMI Naoki1-1/+2
The VCC supply for the BL24C16 EEPROM chip found on Radxa ROCK 5A is vcc_3v3_pmu, which is routed to vcc_3v3_s3 via a zero-ohm resistor. [1] Describe this supply. [1] https://dl.radxa.com/rock5/5a/docs/hw/radxa_rock5a_V1.1_sch.pdf p.4, p.19 Fixes: 89c880808cff8 ("arm64: dts: rockchip: add I2C EEPROM to rock-5a") Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://patch.msgid.link/20251112035133.28753-3-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: Move the EEPROM to correct I2C bus on Radxa ROCK 5AFUKAUMI Naoki1-6/+6
The BL24C16 EEPROM chip found on Radxa ROCK 5A is connected to the i2c0 bus, [1] so move the eeprom node from the i2c2 bus to the i2c0 bus. [1] Link: https://dl.radxa.com/rock5/5a/docs/hw/radxa_rock5a_V1.1_sch.pdf p.19 Fixes: 89c880808cff8 ("arm64: dts: rockchip: add I2C EEPROM to rock-5a") Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://patch.msgid.link/20251112035133.28753-2-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: use SCMI clock id for gpu clock on rk356xHeiko Stuebner1-1/+1
Instead of hard-coding 1, use the more descriptive ID from the binding to reference the SCMI clock for the gpu on rk356x. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251105235408.163282-1-heiko@sntech.de
2025-11-14arm64: dts: rockchip: Remove sdmmc max-frequency on RK3588S EVB1 boardShawn Lin1-1/+0
sdmmc on RK3588S EVB1 could work fine under 200Mhz, no need to limit it to 150Mhz. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://patch.msgid.link/1762844673-123776-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: Remove sdmmc max-frequency for Radxa ROCK 5 ITX/5B/5B+/5TFUKAUMI Naoki2-2/+0
Default max-frequency for sdmmc is "200000000"[1]. Remove redundant definition. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi?h=v6.17#n2013 Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://patch.msgid.link/20251111071730.126238-4-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14arm64: dts: rockchip: Switch microSD card detect to gpio on Radxa ROCK 5 ITX/5CFUKAUMI Naoki4-1/+33
Due to the discussion about cd-gpios and sdmmmc_det pin functionality [1], it would be better to use cd-gpios for now. When the sdmmc controller runtime-suspends, the detection logic inside the controller cannot detect anything anymore, which using the gpio variant fixes. The Rock 5B/5B+/5T already uses cd-gpios, so only get the pinctrl added. [1] https://lore.kernel.org/linux-rockchip/20240912152538.1.I858c2a0bf83606c8b59ba1ab6944978a398d2ac5@changeid/ Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> [amended commit description a bit and squashed the pinctrl patch] Link: https://patch.msgid.link/20251111071730.126238-2-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-14KVM: SVM: Don't skip unrelated instruction if INT3/INTO is replacedOmar Sandoval3-11/+43
When re-injecting a soft interrupt from an INT3, INT0, or (select) INTn instruction, discard the exception and retry the instruction if the code stream is changed (e.g. by a different vCPU) between when the CPU executes the instruction and when KVM decodes the instruction to get the next RIP. As effectively predicted by commit 6ef88d6e36c2 ("KVM: SVM: Re-inject INT3/INTO instead of retrying the instruction"), failure to verify that the correct INTn instruction was decoded can effectively clobber guest state due to decoding the wrong instruction and thus specifying the wrong next RIP. The bug most often manifests as "Oops: int3" panics on static branch checks in Linux guests. Enabling or disabling a static branch in Linux uses the kernel's "text poke" code patching mechanism. To modify code while other CPUs may be executing that code, Linux (temporarily) replaces the first byte of the original instruction with an int3 (opcode 0xcc), then patches in the new code stream except for the first byte, and finally replaces the int3 with the first byte of the new code stream. If a CPU hits the int3, i.e. executes the code while it's being modified, then the guest kernel must look up the RIP to determine how to handle the #BP, e.g. by emulating the new instruction. If the RIP is incorrect, then this lookup fails and the guest kernel panics. The bug reproduces almost instantly by hacking the guest kernel to repeatedly check a static branch[1] while running a drgn script[2] on the host to constantly swap out the memory containing the guest's TSS. [1]: https://gist.github.com/osandov/44d17c51c28c0ac998ea0334edf90b5a [2]: https://gist.github.com/osandov/10e45e45afa29b11e0c7209247afc00b Fixes: 6ef88d6e36c2 ("KVM: SVM: Re-inject INT3/INTO instead of retrying the instruction") Cc: stable@vger.kernel.org Co-developed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Omar Sandoval <osandov@fb.com> Link: https://patch.msgid.link/1cc6dcdf36e3add7ee7c8d90ad58414eeb6c3d34.1762278762.git.osandov@fb.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-11-13Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski79-481/+609
Cross-merge networking fixes after downstream PR (net-6.18-rc6). No conflicts, adjacent changes in: drivers/net/phy/micrel.c 96a9178a29a6 ("net: phy: micrel: lan8814 fix reset of the QSGMII interface") 61b7ade9ba8c ("net: phy: micrel: Add support for non PTP SKUs for lan8814") and a trivial one in tools/testing/selftests/drivers/net/Makefile. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-13arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet supportLad Prabhakar3-0/+218
Enable Ethernet support on the RZ/T2H and RZ/N2H EVKs. Configure the MIIC converter in mode 0x6: Port 0 <-> ETHSW Port 0 Port 1 <-> ETHSW Port 1 Port 2 <-> GMAC2 Port 3 <-> GMAC1 Enable the ETHSS, GMAC1 and GMAC2 nodes. ETHSW support will be added once the switch driver is available. Configure the MIIC converters to map ports according to the selected switching mode, with converters 0 and 1 mapped to switch ports and converters 2 and 3 mapped to GMAC ports. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251110203926.692242-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-13arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable RTCOvidiu Panait1-0/+4
Enable RTC. Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251107210706.45044-5-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-13arm64: dts: renesas: r9a09g057: Add RTC nodeOvidiu Panait1-0/+15
Add RTC node to Renesas RZ/V2H ("R9A09G057") SoC DTSI. Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251107210706.45044-4-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-13arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add NMI pushbutton supportOvidiu Panait1-0/+13
RZ/V2H EVK has a user pushbutton connected to the SoC NMI pin, which can be used to wake up the system from suspend to idle. Add a DT node in the device tree to instantiate the gpio-keys driver for this button. Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251027140651.18367-1-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-13arm64: dts: renesas: rzg3s-smarc: Enable USB supportClaudiu Beznea1-0/+57
Enable USB support (host, device, USB PHYs). Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20251023135810.1688415-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-13arm64: dts: renesas: r9a08g045: Add USB supportClaudiu Beznea1-0/+118
Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset, host and device support. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20251023135810.1688415-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-13arm64: dts: renesas: r9a09g057: Add TSU nodesOvidiu Panait1-0/+75
The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing: - TSU0, which is located near the DRP-AI block - TSU1, which is located near the CPU and DRP-AI block Since TSU1 is physically closer the CPU and the highest temperature spot, it is used for CPU throttling through a passive trip and cooling map. TSU0 is configured only with a critical trip. Add TSU nodes along with thermal zones and keep them enabled in the SoC DTSI. Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251020143107.13974-4-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-13Merge branches 'acpi-cppc' and 'acpi-tables'Rafael J. Wysocki1-1/+1
Merge ACPI CPPC library fixes and an ACPI MRRM table parser fix for 6.18-rc6. * acpi-cppc: ACPI: CPPC: Limit perf ctrs in PCC check only to online CPUs ACPI: CPPC: Perform fast check switch only for online CPUs ACPI: CPPC: Check _CPC validity for only the online CPUs ACPI: CPPC: Detect preferred core availability on online CPUs * acpi-tables: ACPI: MRRM: Fix memory leaks and improve error handling
2025-11-13arm64/sysreg: Add ICH_VMCR_EL2Sascha Bischoff1-0/+21
Add the ICH_VMCR_EL2 register, which is required for the upcoming GICv5 KVM support. This register has two different field encodings, based on if it is used for GICv3 or GICv5-based VMs. The GICv5-specific field encodings are generated with a FEAT_GCIE prefix. This register is already described in the GICv3 KVM code directly. This will be ported across to use the generated encodings as part of an upcoming change. Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2025-11-13arm64/sysreg: Move generation of RES0/RES1/UNKN to functionSascha Bischoff1-12/+14
The RESx and UNKN define generation happens in two places (EndSysreg and EndSysregFields), and was using nearly identical code. Split this out into a function, and call that instead, rather then keeping the dupliated code. There are no changes to the generated sysregs as part of this change. Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2025-11-13arm64/sysreg: Support feature-specific fields with 'Prefix' descriptorSascha Bischoff1-38/+88
Some system register field encodings change based on, for example the in-use architecture features, or the context in which they are accessed. In order to support these different field encodings, introduce the Prefix descriptor (Prefix, EndPrefix) for describing such sysregs. The Prefix descriptor can be used in the following way: Sysreg EXAMPLE 0 1 2 3 4 Prefix FEAT_A Field 63:0 Foo EndPrefix Prefix FEAT_B Field 63:1 Bar Res0 0 EndPrefix Field 63:0 Baz EndSysreg This will generate a single set of system register encodings (REG_, SYS_, ...), and then generate three sets of field definitions for the system register called EXAMPLE. The first set is prefixed by FEAT_A, e.g. FEAT_A_EXAMPLE_Foo. The second set is prefixed by FEAT_B, e.g., FEAT_B_EXAMPLE_Bar. The third set is not given a prefix at all, e.g. EXAMPLE_BAZ. For each set, a corresponding set of defines for Res0, Res1, and Unkn is generated. The intent for the final prefix-less fields is to describe default or legacy field encodings. This ensure that prefixed encodings can be added to already-present sysregs without affecting existing legacy code. Prefixed fields must be defined before those without a prefix, and this is checked by the generator. This ensures consisnt ordering within the sysregs definitions. The Prefix descriptor can be used within Sysreg or SysregFields blocks. Field, Res0, Res1, Unkn, Rax, SignedEnum, Enum can all be used within a Prefix block. Fields and Mapping can not. Fields that vary with features must be described as part of a SysregFields block, instead. Mappings, which are just a code comment, make little sense in this context, and have hence not been included. There are no changes to the generated system register definitions as part of this change. Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Mark Brown <broonie@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2025-11-13arm64/sysreg: Fix checks for incomplete sysreg definitionsSascha Bischoff1-3/+3
The checks for incomplete sysreg definitions were checking if the next_bit was greater than 0, which is incorrect and missed occasions where bit 0 hasn't been defined for a sysreg. The reason is that next_bit is -1 when all bits have been processed (LSB - 1). Change the checks to use >= 0, instead. Also, set next_bit in Mapping to -1 instead of 0 to match these new checks. There are no changes to the generated sysreg definitons as part of this change, and conveniently no definitions lack definitions for bit 0. Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Mark Brown <broonie@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2025-11-13arm64: mm: make linear mapping permission update more robust for patial rangeYang Shi1-3/+3
The commit fcf8dda8cc48 ("arm64: pageattr: Explicitly bail out when changing permissions for vmalloc_huge mappings") made permission update for partial range more robust. But the linear mapping permission update still assumes update the whole range by iterating from the first page all the way to the last page of the area. Make it more robust by updating the linear mapping permission from the page mapped by start address, and update the number of numpages. Reviewed-by: Ryan Roberts <ryan.roberts@arm.com> Reviewed-by: Dev Jain <dev.jain@arm.com> Signed-off-by: Yang Shi <yang@os.amperecomputing.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2025-11-13arm64/mm: Elide TLB flush in certain pte protection transitionsDev Jain1-0/+27
Currently arm64 does an unconditional TLB flush in mprotect(). This is not required for some cases, for example, when changing from PROT_NONE to PROT_READ | PROT_WRITE (a real usecase - glibc malloc does this to emulate growing into the non-main heaps), and unsetting uffd-wp in a range. Therefore, implement pte_needs_flush() for arm64, which is already implemented by some other arches as well. Running a userspace program changing permissions back and forth between PROT_NONE and PROT_READ | PROT_WRITE, and measuring the average time taken for the none->rw transition, I get a reduction from 3.2 microseconds to 2.85 microseconds, giving a 12.3% improvement. Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Dev Jain <dev.jain@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2025-11-13arm64: dts: ti: k3-am62l: add initial reference board fileVignesh Raghavendra2-0/+364
Add the initial board file for the AM62L3's Evaluation Module. Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://patch.msgid.link/20251105-am62lx-v8-3-496f353e8237@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-11-13arm64: dts: ti: k3-am62l: add initial infrastructureVignesh Raghavendra5-0/+908
Add the initial infrastructure needed for the AM62L. ALl of which can be found in the Technical Reference Manual (TRM) located here: https://www.ti.com/lit/pdf/sprujb4 Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://patch.msgid.link/20251105-am62lx-v8-2-496f353e8237@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-11-13KVM: TDX: Use struct_size to simplify tdx_get_capabilities()Sean Christopherson1-9/+4
Use struct_size() instead of manually calculating the number of bytes to allocate for 'caps', including the nested flexible array, and copy all of 'caps' to user space with a single copy_to_user() call (thanks to the full size being provided by struct_size()). Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Tested-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Link: https://patch.msgid.link/20251017213914.167301-1-thorsten.blum@linux.dev [sean: separate from swap of get_user() vs. kzalloc() ordering] Signed-off-by: Sean Christopherson <seanjc@google.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-06-05 04:45:12 +0300